<AVRPART><MODULE_LIST>[ADMIN:MEMORY:CORE:INTERRUPT_VECTOR:PACKAGE:POWER:PROGVOLT:FUSE:PROGRAMMING:IO_MODULE:ICE_SETTINGS:LOCKBIT]</MODULE_LIST><ADMIN>
<PART_NAME>AT90S4433</PART_NAME>
<SPEED>8MHZ</SPEED>
<BUILD>196</BUILD>
<RELEASE_STATUS>RELEASED</RELEASE_STATUS>
<SIGNATURE>
<ADDR000>$1E</ADDR000>
<ADDR001>$92</ADDR001>
<ADDR002>$03</ADDR002>
</SIGNATURE>
</ADMIN>
<MEMORY>
<ID>AVRSimMemory8bit.SimMemory8bit</ID>
<PROG_FLASH>4096</PROG_FLASH>
<EEPROM>256</EEPROM>
<INT_SRAM>
<SIZE>128</SIZE>
<START_ADDR>$60</START_ADDR>
</INT_SRAM>
<EXT_SRAM>
<SIZE>0</SIZE>
<START_ADDR>NA</START_ADDR>
</EXT_SRAM>
<IO_MEMORY>
<IO_START_ADDR>$00</IO_START_ADDR>
<IO_STOP_ADDR>$3F</IO_STOP_ADDR>
<EXT_IO_START_ADDR>NA</EXT_IO_START_ADDR>
<EXT_IO_STOP_ADDR>NA</EXT_IO_STOP_ADDR>
<MEM_START_ADDR>$20</MEM_START_ADDR>
<MEM_STOP_ADDR>$5F</MEM_STOP_ADDR>
<SREG>
<IO_ADDR>$3F</IO_ADDR>
<MEM_ADDR>$5F</MEM_ADDR>
<C_MASK>0x01</C_MASK><Z_MASK>0x02</Z_MASK><N_MASK>0x04</N_MASK><V_MASK>0x08</V_MASK><S_MASK>0x10</S_MASK><H_MASK>0x20</H_MASK><T_MASK>0x40</T_MASK><I_MASK>0x80</I_MASK></SREG>
<SP>
<IO_ADDR>$3D</IO_ADDR>
<MEM_ADDR>$5D</MEM_ADDR>
<SP0_MASK>0x01</SP0_MASK><SP1_MASK>0x02</SP1_MASK><SP2_MASK>0x04</SP2_MASK><SP3_MASK>0x08</SP3_MASK><SP4_MASK>0x10</SP4_MASK><SP5_MASK>0x20</SP5_MASK><SP6_MASK>0x40</SP6_MASK><SP7_MASK>0x80</SP7_MASK></SP>
<GIMSK>
<IO_ADDR>$3B</IO_ADDR>
<MEM_ADDR>$5B</MEM_ADDR>
<INT0_MASK>0x40</INT0_MASK><INT1_MASK>0x80</INT1_MASK></GIMSK>
<GIFR>
<IO_ADDR>$3A</IO_ADDR>
<MEM_ADDR>$5A</MEM_ADDR>
<INTF0_MASK>0x40</INTF0_MASK><INTF1_MASK>0x80</INTF1_MASK></GIFR>
<TIMSK>
<IO_ADDR>$39</IO_ADDR>
<MEM_ADDR>$59</MEM_ADDR>
<TOIE0_MASK>0x02</TOIE0_MASK><TICIE1_MASK>0x08</TICIE1_MASK><OCIE1_MASK>0x40</OCIE1_MASK><TOIE1_MASK>0x80</TOIE1_MASK></TIMSK>
<TIFR>
<IO_ADDR>$38</IO_ADDR>
<MEM_ADDR>$58</MEM_ADDR>
<TOV0_MASK>0x02</TOV0_MASK><ICF1_MASK>0x08</ICF1_MASK><OCF1_MASK>0x40</OCF1_MASK><TOV1_MASK>0x80</TOV1_MASK></TIFR>
<MCUCR>
<IO_ADDR>$35</IO_ADDR>
<MEM_ADDR>$55</MEM_ADDR>
<ISC00_MASK>0x01</ISC00_MASK><ISC01_MASK>0x02</ISC01_MASK><ISC10_MASK>0x04</ISC10_MASK><ISC11_MASK>0x08</ISC11_MASK><SM_MASK>0x10</SM_MASK><SE_MASK>0x20</SE_MASK></MCUCR>
<MCUSR>
<IO_ADDR>$34</IO_ADDR>
<MEM_ADDR>$54</MEM_ADDR>
<PORF_MASK>0x01</PORF_MASK><EXTRF_MASK>0x02</EXTRF_MASK><BORF_MASK>0x04</BORF_MASK><WDRF_MASK>0x08</WDRF_MASK></MCUSR>
<TCCR0>
<IO_ADDR>$33</IO_ADDR>
<MEM_ADDR>$53</MEM_ADDR>
<CS00_MASK>0x01</CS00_MASK><CS01_MASK>0x02</CS01_MASK><CS02_MASK>0x04</CS02_MASK></TCCR0>
<TCNT0>
<IO_ADDR>$32</IO_ADDR>
<MEM_ADDR>$52</MEM_ADDR>
<TCNT00_MASK>0x01</TCNT00_MASK><TCNT01_MASK>0x02</TCNT01_MASK><TCNT02_MASK>0x04</TCNT02_MASK><TCNT03_MASK>0x08</TCNT03_MASK><TCNT04_MASK>0x10</TCNT04_MASK><TCNT05_MASK>0x20</TCNT05_MASK><TCNT06_MASK>0x40</TCNT06_MASK><TCNT07_MASK>0x80</TCNT07_MASK></TCNT0>
<TCCR1A>
<IO_ADDR>$2F</IO_ADDR>
<MEM_ADDR>$4F</MEM_ADDR>
<PWM10_MASK>0x01</PWM10_MASK><PWM11_MASK>0x02</PWM11_MASK><COM10_MASK>0x40</COM10_MASK><COM11_MASK>0x80</COM11_MASK></TCCR1A>
<TCCR1B>
<IO_ADDR>$2E</IO_ADDR>
<MEM_ADDR>$4E</MEM_ADDR>
<CS10_MASK>0x01</CS10_MASK><CS11_MASK>0x02</CS11_MASK><CS12_MASK>0x04</CS12_MASK><CTC1_MASK>0x08</CTC1_MASK><ICES1_MASK>0x40</ICES1_MASK><ICNC1_MASK>0x80</ICNC1_MASK></TCCR1B>
<TCNT1H>
<IO_ADDR>$2D</IO_ADDR>
<MEM_ADDR>$4D</MEM_ADDR>
<TCNT1H0_MASK>0x01</TCNT1H0_MASK><TCNT1H1_MASK>0x02</TCNT1H1_MASK><TCNT1H2_MASK>0x04</TCNT1H2_MASK><TCNT1H3_MASK>0x08</TCNT1H3_MASK><TCNT1H4_MASK>0x10</TCNT1H4_MASK><TCNT1H5_MASK>0x20</TCNT1H5_MASK><TCNT1H6_MASK>0x40</TCNT1H6_MASK><TCNT1H7_MASK>0x80</TCNT1H7_MASK></TCNT1H>
<TCNT1L>
<IO_ADDR>$2C</IO_ADDR>
<MEM_ADDR>$4C</MEM_ADDR>
<TCNT1L0_MASK>0x01</TCNT1L0_MASK><TCNT1L1_MASK>0x02</TCNT1L1_MASK><TCNT1L2_MASK>0x04</TCNT1L2_MASK><TCNT1L3_MASK>0x08</TCNT1L3_MASK><TCNT1L4_MASK>0x10</TCNT1L4_MASK><TCNT1L5_MASK>0x20</TCNT1L5_MASK><TCNT1L6_MASK>0x40</TCNT1L6_MASK><TCNT1L7_MASK>0x80</TCNT1L7_MASK></TCNT1L>
<OCR1H>
<IO_ADDR>$2B</IO_ADDR>
<MEM_ADDR>$4B</MEM_ADDR>
<OCR1AH0_MASK>0x01</OCR1AH0_MASK><OCR1AH1_MASK>0x02</OCR1AH1_MASK><OCR1AH2_MASK>0x04</OCR1AH2_MASK><OCR1AH3_MASK>0x08</OCR1AH3_MASK><OCR1AH4_MASK>0x10</OCR1AH4_MASK><OCR1AH5_MASK>0x20</OCR1AH5_MASK><OCR1AH6_MASK>0x40</OCR1AH6_MASK><OCR1AH7_MASK>0x80</OCR1AH7_MASK></OCR1H>
<OCR1L>
<IO_ADDR>$2A</IO_ADDR>
<MEM_ADDR>$4A</MEM_ADDR>
<OCR1AL0_MASK>0x01</OCR1AL0_MASK><OCR1AL1_MASK>0x02</OCR1AL1_MASK><OCR1AL2_MASK>0x04</OCR1AL2_MASK><OCR1AL3_MASK>0x08</OCR1AL3_MASK><OCR1AL4_MASK>0x10</OCR1AL4_MASK><OCR1AL5_MASK>0x20</OCR1AL5_MASK><OCR1AL6_MASK>0x40</OCR1AL6_MASK><OCR1AL7_MASK>0x80</OCR1AL7_MASK></OCR1L>
<ICR1H>
<IO_ADDR>$27</IO_ADDR>
<MEM_ADDR>$47</MEM_ADDR>
<ICR1H0_MASK>0x01</ICR1H0_MASK><ICR1H1_MASK>0x02</ICR1H1_MASK><ICR1H2_MASK>0x04</ICR1H2_MASK><ICR1H3_MASK>0x08</ICR1H3_MASK><ICR1H4_MASK>0x10</ICR1H4_MASK><ICR1H5_MASK>0x20</ICR1H5_MASK><ICR1H6_MASK>0x40</ICR1H6_MASK><ICR1H7_MASK>0x80</ICR1H7_MASK></ICR1H>
<ICR1L>
<IO_ADDR>$26</IO_ADDR>
<MEM_ADDR>$46</MEM_ADDR>
<ICR1L0_MASK>0x01</ICR1L0_MASK><ICR1L1_MASK>0x02</ICR1L1_MASK><ICR1L2_MASK>0x04</ICR1L2_MASK><ICR1L3_MASK>0x08</ICR1L3_MASK><ICR1L4_MASK>0x10</ICR1L4_MASK><ICR1L5_MASK>0x20</ICR1L5_MASK><ICR1L6_MASK>0x40</ICR1L6_MASK><ICR1L7_MASK>0x80</ICR1L7_MASK></ICR1L>
<WDTCR>
<IO_ADDR>$21</IO_ADDR>
<MEM_ADDR>$41</MEM_ADDR>
<WDP0_MASK>0x01</WDP0_MASK><WDP1_MASK>0x02</WDP1_MASK><WDP2_MASK>0x04</WDP2_MASK><WDE_MASK>0x08</WDE_MASK><WDTOE_MASK>0x10</WDTOE_MASK></WDTCR>
<EEAR>
<IO_ADDR>$1E</IO_ADDR>
<MEM_ADDR>$3E</MEM_ADDR>
<EEAR0_MASK>0x01</EEAR0_MASK><EEAR1_MASK>0x02</EEAR1_MASK><EEAR2_MASK>0x04</EEAR2_MASK><EEAR3_MASK>0x08</EEAR3_MASK><EEAR4_MASK>0x10</EEAR4_MASK><EEAR5_MASK>0x20</EEAR5_MASK><EEAR6_MASK>0x40</EEAR6_MASK><EEAR7_MASK>0x80</EEAR7_MASK></EEAR>
<EEDR>
<IO_ADDR>$1D</IO_ADDR>
<MEM_ADDR>$3D</MEM_ADDR>
<EEDR0_MASK>0x01</EEDR0_MASK><EEDR1_MASK>0x02</EEDR1_MASK><EEDR2_MASK>0x04</EEDR2_MASK><EEDR3_MASK>0x08</EEDR3_MASK><EEDR4_MASK>0x10</EEDR4_MASK><EEDR5_MASK>0x20</EEDR5_MASK><EEDR6_MASK>0x40</EEDR6_MASK><EEDR7_MASK>0x80</EEDR7_MASK></EEDR>
<EECR>
<IO_ADDR>$1C</IO_ADDR>
<MEM_ADDR>$3C</MEM_ADDR>
<EERE_MASK>0x01</EERE_MASK><EEWE_MASK>0x02</EEWE_MASK><EEMWE_MASK>0x04</EEMWE_MASK><EERIE_MASK>0x08</EERIE_MASK></EECR>
<PORTB>
<IO_ADDR>$18</IO_ADDR>
<MEM_ADDR>$38</MEM_ADDR>
<MASK>$3f</MASK>
<PORTB0_MASK>0x01</PORTB0_MASK><PORTB1_MASK>0x02</PORTB1_MASK><PORTB2_MASK>0x04</PORTB2_MASK><PORTB3_MASK>0x08</PORTB3_MASK><PORTB4_MASK>0x10</PORTB4_MASK><PORTB5_MASK>0x20</PORTB5_MASK></PORTB>
<DDRB>
<IO_ADDR>$17</IO_ADDR>
<MEM_ADDR>$37</MEM_ADDR>
<DDB0_MASK>0x01</DDB0_MASK><DDB1_MASK>0x02</DDB1_MASK><DDB2_MASK>0x04</DDB2_MASK><DDB3_MASK>0x08</DDB3_MASK><DDB4_MASK>0x10</DDB4_MASK><DDB5_MASK>0x20</DDB5_MASK></DDRB>
<PINB>
<IO_ADDR>$16</IO_ADDR>
<MEM_ADDR>$36</MEM_ADDR>
<PINB0_MASK>0x01</PINB0_MASK><PINB1_MASK>0x02</PINB1_MASK><PINB2_MASK>0x04</PINB2_MASK><PINB3_MASK>0x08</PINB3_MASK><PINB4_MASK>0x10</PINB4_MASK><PINB5_MASK>0x20</PINB5_MASK></PINB>
<PORTC>
<IO_ADDR>$15</IO_ADDR>
<MEM_ADDR>$35</MEM_ADDR>
<MASK>$3f</MASK>
<PORTC0_MASK>0x01</PORTC0_MASK><PORTC1_MASK>0x02</PORTC1_MASK><PORTC2_MASK>0x04</PORTC2_MASK><PORTC3_MASK>0x08</PORTC3_MASK><PORTC4_MASK>0x10</PORTC4_MASK><PORTC5_MASK>0x20</PORTC5_MASK></PORTC>
<DDRC>
<IO_ADDR>$14</IO_ADDR>
<MEM_ADDR>$34</MEM_ADDR>
<DDC0_MASK>0x01</DDC0_MASK><DDC1_MASK>0x02</DDC1_MASK><DDC2_MASK>0x04</DDC2_MASK><DDC3_MASK>0x08</DDC3_MASK><DDC4_MASK>0x10</DDC4_MASK><DDC5_MASK>0x20</DDC5_MASK></DDRC>
<PINC>
<IO_ADDR>$13</IO_ADDR>
<MEM_ADDR>$33</MEM_ADDR>
<PINC0_MASK>0x01</PINC0_MASK><PINC1_MASK>0x02</PINC1_MASK><PINC2_MASK>0x04</PINC2_MASK><PINC3_MASK>0x08</PINC3_MASK><PINC4_MASK>0x10</PINC4_MASK><PINC5_MASK>0x20</PINC5_MASK></PINC>
<PORTD>
<IO_ADDR>$12</IO_ADDR>
<MEM_ADDR>$32</MEM_ADDR>
<MASK>$ff</MASK>
<PORTD0_MASK>0x01</PORTD0_MASK><PORTD1_MASK>0x02</PORTD1_MASK><PORTD2_MASK>0x04</PORTD2_MASK><PORTD3_MASK>0x08</PORTD3_MASK><PORTD4_MASK>0x10</PORTD4_MASK><PORTD5_MASK>0x20</PORTD5_MASK><PORTD6_MASK>0x40</PORTD6_MASK><PORTD7_MASK>0x80</PORTD7_MASK></PORTD>
<DDRD>
<IO_ADDR>$11</IO_ADDR>
<MEM_ADDR>$31</MEM_ADDR>
<DDD0_MASK>0x01</DDD0_MASK><DDD1_MASK>0x02</DDD1_MASK><DDD2_MASK>0x04</DDD2_MASK><DDD3_MASK>0x08</DDD3_MASK><DDD4_MASK>0x10</DDD4_MASK><DDD5_MASK>0x20</DDD5_MASK><DDD6_MASK>0x40</DDD6_MASK><DDD7_MASK>0x80</DDD7_MASK></DDRD>
<PIND>
<IO_ADDR>$10</IO_ADDR>
<MEM_ADDR>$30</MEM_ADDR>
<PIND0_MASK>0x01</PIND0_MASK><PIND1_MASK>0x02</PIND1_MASK><PIND2_MASK>0x04</PIND2_MASK><PIND3_MASK>0x08</PIND3_MASK><PIND4_MASK>0x10</PIND4_MASK><PIND5_MASK>0x20</PIND5_MASK><PIND6_MASK>0x40</PIND6_MASK><PIND7_MASK>0x80</PIND7_MASK></PIND>
<SPDR>
<IO_ADDR>$0F</IO_ADDR>
<MEM_ADDR>$2F</MEM_ADDR>
<SPDR0_MASK>0x01</SPDR0_MASK><SPDR1_MASK>0x02</SPDR1_MASK><SPDR2_MASK>0x04</SPDR2_MASK><SPDR3_MASK>0x08</SPDR3_MASK><SPDR4_MASK>0x10</SPDR4_MASK><SPDR5_MASK>0x20</SPDR5_MASK><SPDR6_MASK>0x40</SPDR6_MASK><SPDR7_MASK>0x80</SPDR7_MASK></SPDR>
<SPSR>
<IO_ADDR>$0E</IO_ADDR>
<MEM_ADDR>$2E</MEM_ADDR>
<WCOL_MASK>0x40</WCOL_MASK><SPIF_MASK>0x80</SPIF_MASK></SPSR>
<SPCR>
<IO_ADDR>$0D</IO_ADDR>
<MEM_ADDR>$2D</MEM_ADDR>
<SPR0_MASK>0x01</SPR0_MASK><SPR1_MASK>0x02</SPR1_MASK><CPHA_MASK>0x04</CPHA_MASK><CPOL_MASK>0x08</CPOL_MASK><MSTR_MASK>0x10</MSTR_MASK><DORD_MASK>0x20</DORD_MASK><SPE_MASK>0x40</SPE_MASK><SPIE_MASK>0x80</SPIE_MASK></SPCR>
<UDR>
<IO_ADDR>$0C</IO_ADDR>
<MEM_ADDR>$2C</MEM_ADDR>
<UDR0_MASK>0x01</UDR0_MASK><UDR1_MASK>0x02</UDR1_MASK><UDR2_MASK>0x04</UDR2_MASK><UDR3_MASK>0x08</UDR3_MASK><UDR4_MASK>0x10</UDR4_MASK><UDR5_MASK>0x20</UDR5_MASK><UDR6_MASK>0x40</UDR6_MASK><UDR7_MASK>0x80</UDR7_MASK></UDR>
<UCSRA>
<IO_ADDR>$0B</IO_ADDR>
<MEM_ADDR>$2B</MEM_ADDR>
<MPCM_MASK>0x01</MPCM_MASK><OR_MASK>0x08</OR_MASK><FE_MASK>0x10</FE_MASK><UDRE_MASK>0x20</UDRE_MASK><TXC_MASK>0x40</TXC_MASK><RXC_MASK>0x80</RXC_MASK></UCSRA>
<UCSRB>
<IO_ADDR>$0A</IO_ADDR>
<MEM_ADDR>$2A</MEM_ADDR>
<TXB8_MASK>0x01</TXB8_MASK><RXB8_MASK>0x02</RXB8_MASK><CHR9_MASK>0x04</CHR9_MASK><TXEN_MASK>0x08</TXEN_MASK><RXEN_MASK>0x10</RXEN_MASK><UDRIE_MASK>0x20</UDRIE_MASK><TXCIE_MASK>0x40</TXCIE_MASK><RXCIE_MASK>0x80</RXCIE_MASK></UCSRB>
<UBRR>
<IO_ADDR>$09</IO_ADDR>
<MEM_ADDR>$29</MEM_ADDR>
<UBRR0_MASK>0x01</UBRR0_MASK><UBRR1_MASK>0x02</UBRR1_MASK><UBRR2_MASK>0x04</UBRR2_MASK><UBRR3_MASK>0x08</UBRR3_MASK><UBRR4_MASK>0x10</UBRR4_MASK><UBRR5_MASK>0x20</UBRR5_MASK><UBRR6_MASK>0x40</UBRR6_MASK><UBRR7_MASK>0x80</UBRR7_MASK></UBRR>
<ACSR>
<IO_ADDR>$08</IO_ADDR>
<MEM_ADDR>$28</MEM_ADDR>
<ACIS0_MASK>0x01</ACIS0_MASK><ACIS1_MASK>0x02</ACIS1_MASK><ACIC_MASK>0x04</ACIC_MASK><ACIE_MASK>0x08</ACIE_MASK><ACI_MASK>0x10</ACI_MASK><ACO_MASK>0x20</ACO_MASK><AINBG_MASK>0x40</AINBG_MASK><ACD_MASK>0x80</ACD_MASK></ACSR>
<ADMUX>
<IO_ADDR>$07</IO_ADDR>
<MEM_ADDR>$27</MEM_ADDR>
<MUX0_MASK>0x01</MUX0_MASK><MUX1_MASK>0x02</MUX1_MASK><MUX2_MASK>0x04</MUX2_MASK><ADCBG_MASK>0x40</ADCBG_MASK></ADMUX>
<ADCSR>
<IO_ADDR>$06</IO_ADDR>
<MEM_ADDR>$26</MEM_ADDR>
<ADPS0_MASK>0x01</ADPS0_MASK><ADPS1_MASK>0x02</ADPS1_MASK><ADPS2_MASK>0x04</ADPS2_MASK><ADIE_MASK>0x08</ADIE_MASK><ADIF_MASK>0x10</ADIF_MASK><ADFR_MASK>0x20</ADFR_MASK><ADSC_MASK>0x40</ADSC_MASK><ADEN_MASK>0x80</ADEN_MASK></ADCSR>
<ADCH>
<IO_ADDR>$05</IO_ADDR>
<MEM_ADDR>$25</MEM_ADDR>
<ADC8_MASK>0x01</ADC8_MASK><ADC9_MASK>0x02</ADC9_MASK></ADCH>
<ADCL>
<IO_ADDR>$04</IO_ADDR>
<MEM_ADDR>$24</MEM_ADDR>
<ADC0_MASK>0x01</ADC0_MASK><ADC1_MASK>0x02</ADC1_MASK><ADC2_MASK>0x04</ADC2_MASK><ADC3_MASK>0x08</ADC3_MASK><ADC4_MASK>0x10</ADC4_MASK><ADC5_MASK>0x20</ADC5_MASK><ADC6_MASK>0x40</ADC6_MASK><ADC7_MASK>0x80</ADC7_MASK></ADCL>
<UBRRHI>
<IO_ADDR>$03</IO_ADDR>
<MEM_ADDR>$23</MEM_ADDR>
<UBRRHI0_MASK>0x01</UBRRHI0_MASK><UBRRHI1_MASK>0x02</UBRRHI1_MASK><UBRRHI2_MASK>0x04</UBRRHI2_MASK><UBRRHI3_MASK>0x08</UBRRHI3_MASK></UBRRHI>
</IO_MEMORY>
</MEMORY>
<CORE>
<CORE_VERSION>V1</CORE_VERSION>
<ID>AVRSimCoreV1.SimCoreV1</ID>
<NEW_INSTRUCTIONS>[]</NEW_INSTRUCTIONS>
<INSTRUCTIONS_NOT_SUPPORTED>[]</INSTRUCTIONS_NOT_SUPPORTED>
<RAMP_REGISTERS>[0x0023:0x0034:0x0054]</RAMP_REGISTERS>
<GP_REG_FILE>
<NMB_REG>32</NMB_REG>
<START_ADDR>$00</START_ADDR>
<X_REG_HIGH>$1B</X_REG_HIGH>
<X_REG_LOW>$1A</X_REG_LOW>
<Y_REG_HIGH>$1D</Y_REG_HIGH>
<Y_REG_LOW>$1C</Y_REG_LOW>
<Z_REG_HIGH>$1F</Z_REG_HIGH>
<Z_REG_LOW>$1E</Z_REG_LOW>
</GP_REG_FILE>
</CORE>
<INTERRUPT_VECTOR>
<NMB_VECTORS>14</NMB_VECTORS>
<VECTOR1>
<PROGRAM_ADDRESS>$000</PROGRAM_ADDRESS>
<SOURCE>RESET</SOURCE>
<DEFINITION>External Reset, Power-on Reset and Watchdog Reset</DEFINITION>
</VECTOR1>
<VECTOR2>
<PROGRAM_ADDRESS>$001</PROGRAM_ADDRESS>
<SOURCE>INT0</SOURCE>
<DEFINITION>External Interrupt 0</DEFINITION>
</VECTOR2>
<VECTOR3>
<PROGRAM_ADDRESS>$002</PROGRAM_ADDRESS>
<SOURCE>INT1</SOURCE>
<DEFINITION>External Interrupt 1</DEFINITION>
</VECTOR3>
<VECTOR4>
<PROGRAM_ADDRESS>$003</PROGRAM_ADDRESS>
<SOURCE>TIMER1_CAPT</SOURCE>
<DEFINITION>Timer/Counter Capture Event</DEFINITION>
</VECTOR4>
<VECTOR5>
<PROGRAM_ADDRESS>$004</PROGRAM_ADDRESS>
<SOURCE>TIMER1_COMP</SOURCE>
<DEFINITION>Timer/Counter1 Compare Match</DEFINITION>
</VECTOR5>
<VECTOR6>
<PROGRAM_ADDRESS>$005</PROGRAM_ADDRESS>
<SOURCE>TIMER1_OVF</SOURCE>
<DEFINITION>Timer/Counter1 Overflow</DEFINITION>
</VECTOR6>
<VECTOR7>
<PROGRAM_ADDRESS>$006</PROGRAM_ADDRESS>
<SOURCE>TIMER0_OVF</SOURCE>
<DEFINITION>Timer/Counter0 Overflow</DEFINITION>
</VECTOR7>
<VECTOR8>
<PROGRAM_ADDRESS>$007</PROGRAM_ADDRESS>
<SOURCE>SPI,STC</SOURCE>
<DEFINITION>Serial Transfer Complete</DEFINITION>
</VECTOR8>
<VECTOR9>
<PROGRAM_ADDRESS>$008</PROGRAM_ADDRESS>
<SOURCE>UART,RX</SOURCE>
<DEFINITION>UART, Rx Complete</DEFINITION>
</VECTOR9>
<VECTOR10>
<PROGRAM_ADDRESS>$009</PROGRAM_ADDRESS>
<SOURCE>UART,UDRE</SOURCE>
<DEFINITION>UART Data Register Empty</DEFINITION>
</VECTOR10>
<VECTOR11>
<PROGRAM_ADDRESS>$00A</PROGRAM_ADDRESS>
<SOURCE>UART, TX</SOURCE>
<DEFINITION>UART, Tx Complete</DEFINITION>
</VECTOR11>
<VECTOR12>
<PROGRAM_ADDRESS>$00B</PROGRAM_ADDRESS>
<SOURCE>ADC</SOURCE>
<DEFINITION>ADC Conversion Complete</DEFINITION>
</VECTOR12>
<VECTOR13>
<PROGRAM_ADDRESS>$00C</PROGRAM_ADDRESS>
<SOURCE>EE_RDY</SOURCE>
<DEFINITION>EEPROM Ready</DEFINITION>
</VECTOR13>
<VECTOR14>
<PROGRAM_ADDRESS>$00D</PROGRAM_ADDRESS>
<SOURCE>ANA_COMP</SOURCE>
<DEFINITION>Analog Comparator</DEFINITION>
</VECTOR14>
</INTERRUPT_VECTOR>
<PACKAGE>
<PACKAGES>[TQFP]</PACKAGES>
<TQFP>
<NMB_PIN>32</NMB_PIN>
<PIN1>
<NAME>[INT1:PD3]</NAME>
<TEXT/>
</PIN1>
<PIN2>
<NAME>[T0:PD4]</NAME>
<TEXT/>
</PIN2>
<PIN3>
<NAME>[NC]</NAME>
<TEXT/>
</PIN3>
<PIN4>
<NAME>[VCC]</NAME>
<TEXT/>
</PIN4>
<PIN5>
<NAME>[GND]</NAME>
<TEXT/>
</PIN5>
<PIN6>
<NAME>[NC]</NAME>
<TEXT/>
</PIN6>
<PIN7>
<NAME>[XTAL1]</NAME>
<TEXT/>
</PIN7>
<PIN8>
<NAME>[XTAL2]</NAME>
<TEXT/>
</PIN8>
<PIN9>
<NAME>[T1:PD5]</NAME>
<TEXT/>
</PIN9>
<PIN10>
<NAME>[AIN0:PD6]</NAME>
<TEXT/>
</PIN10>
<PIN11>
<NAME>[AIN1:PD7]</NAME>
<TEXT/>
</PIN11>
<PIN12>
<NAME>[ICP:PB0]</NAME>
<TEXT/>
</PIN12>
<PIN13>
<NAME>[OC1:PB1]</NAME>
<TEXT/>
</PIN13>
<PIN14>
<NAME>[SS:PB2]</NAME>
<TEXT/>
</PIN14>
<PIN15>
<NAME>[MOS1:PB3]</NAME>
<TEXT/>
</PIN15>
<PIN16>
<NAME>[MOS0:PB4]</NAME>
<TEXT/>
</PIN16>
<PIN17>
<NAME>[SCK:PB5]</NAME>
<TEXT/>
</PIN17>
<PIN18>
<NAME>[AVCC]</NAME>
<TEXT/>
</PIN18>
<PIN19>
<NAME>[NC]</NAME>
<TEXT/>
</PIN19>
<PIN20>
<NAME>[AREF]</NAME>
<TEXT/>
</PIN20>
<PIN21>
<NAME>[AGND]</NAME>
<TEXT/>
</PIN21>
<PIN22>
<NAME>[NC]</NAME>
<TEXT/>
</PIN22>
<PIN23>
<NAME>[PC0:ADC0]</NAME>
<TEXT/>
</PIN23>
<PIN24>
<NAME>[PC1:ADC1]</NAME>
<TEXT/>
</PIN24>
<PIN25>
<NAME>[PC2:ADC2]</NAME>
<TEXT/>
</PIN25>
<PIN26>
<NAME>[PC3:ADC3]</NAME>
<TEXT/>
</PIN26>
<PIN27>
<NAME>[PC4:ADC4]</NAME>
<TEXT/>
</PIN27>
<PIN28>
<NAME>[PC5:ADC5]</NAME>
<TEXT/>
</PIN28>
<PIN29>
<NAME>[RESET]</NAME>
<TEXT/>
</PIN29>
<PIN30>
<NAME>[PD0:RXD]</NAME>
<TEXT/>
</PIN30>
<PIN31>
<NAME>[PD1:TXD]</NAME>
<TEXT/>
</PIN31>
<PIN32>
<NAME>[PD2:INT0]</NAME>
<TEXT/>
</PIN32>
</TQFP>
</PACKAGE>
<POWER>
<CLOCK>4MHz</CLOCK>
<TEMP>25C</TEMP>
<ACTIVE>3.4mA</ACTIVE>
<IDLE>1.4mA</IDLE>
<POWER_DOWN><1uA</POWER_DOWN>
</POWER>
<PROGVOLT>
<SER_PROG_MIN_V>2.7</SER_PROG_MIN_V>
<SER_PROG_MAX_V>6.0</SER_PROG_MAX_V>
<PAR_PROG_MIN_V>4.5</PAR_PROG_MIN_V>
<PAR_PROG_MAX_V>5.5</PAR_PROG_MAX_V>
</PROGVOLT>
<FUSE>
<LIST>[LOW]</LIST>
<ICON/>
<ID/>
<TEXT/>
<LOW>
<NMB_TEXT>12</NMB_TEXT>
<TEXT1>
<MASK>0x20</MASK>
<VALUE>0x00</VALUE>
<TEXT>Serial program downloading (SPI) enabled</TEXT>
</TEXT1>
<TEXT2>
<MASK>0x08</MASK>
<VALUE>0x00</VALUE>
<TEXT>Brown-out detection enabled</TEXT>
</TEXT2>
<TEXT3>
<MASK>0x10</MASK>
<VALUE>0x10</VALUE>
<TEXT>Brown-out detection level at VCC=2.7V</TEXT>
</TEXT3>
<TEXT4>
<MASK>0x10</MASK>
<VALUE>0x00</VALUE>
<TEXT>Brown-out detection level at VCC=4.0V</TEXT>
</TEXT4>
<TEXT5>
<MASK>0x07</MASK>
<VALUE>0x00</VALUE>
<TEXT>External Clock; slowly rising power</TEXT>
</TEXT5>
<TEXT6>
<MASK>0x07</MASK>
<VALUE>0x01</VALUE>
<TEXT>External Clock; BOD Enabled or power-on reset</TEXT>
</TEXT6>
<TEXT7>
<MASK>0x07</MASK>
<VALUE>0x02</VALUE>
<TEXT>Crystal Oscillator; default value</TEXT>
</TEXT7>
<TEXT8>
<MASK>0x07</MASK>
<VALUE>0x03</VALUE>
<TEXT>Crystal Oscillator; fast rising power</TEXT>
</TEXT8>
<TEXT9>
<MASK>0x07</MASK>
<VALUE>0x04</VALUE>
<TEXT>Crystal Oscillator; BOD Enabled or power-on reset</TEXT>
</TEXT9>
<TEXT10>
<MASK>0x07</MASK>
<VALUE>0x05</VALUE>
<TEXT>Ceramic Resonator</TEXT>
</TEXT10>
<TEXT11>
<MASK>0x07</MASK>
<VALUE>0x06</VALUE>
<TEXT>Ceramic Resonator; fast rising power</TEXT>
</TEXT11>
<TEXT12>
<MASK>0x07</MASK>
<VALUE>0x07</VALUE>
<TEXT>Ceramic Resonator; BOD Enabled or power-on reset</TEXT>
</TEXT12>
</LOW>
</FUSE><PROGRAMMING>
<ISPInterface>
<FuseProgMask>0xDF</FuseProgMask>
<FuseWarning>0,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!</FuseWarning>
<FuseWarning>0,0x08,0x00,WARNING! Unless target power is controlled by STK500, power will have to cycled manually for BODEN programming to take effect!</FuseWarning>
</ISPInterface>
<HVInterface>
<FuseWarning>0,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!</FuseWarning>
<FuseWarning>0,0x08,0x00,WARNING! Unless target power is controlled by STK500, power will have to cycled manually for BODEN programming to take effect!</FuseWarning>
</HVInterface>
<OscCal>
</OscCal>
<FlashPageSize>0</FlashPageSize>
<EepromPageSize>0</EepromPageSize>
</PROGRAMMING>
<LOCKBIT>
<ICON/>
<ID/>
<TEXT>[LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled</TEXT>
<NMB_TEXT>3</NMB_TEXT>
<NMB_LOCK_BITS>2</NMB_LOCK_BITS>
<TEXT1>
<MASK>0x06</MASK>
<VALUE>0x06</VALUE>
<TEXT>Mode 1: No memory lock features enabled</TEXT>
</TEXT1>
<TEXT2>
<MASK>0x06</MASK>
<VALUE>0x04</VALUE>
<TEXT>Mode 2: Further programming disabled</TEXT>
</TEXT2>
<TEXT3>
<MASK>0x06</MASK>
<VALUE>0x00</VALUE>
<TEXT>Mode 3: Further programming and verification disabled</TEXT>
</TEXT3>
<LOCKBIT0>
<NAME>LB1</NAME>
<TEXT>Lockbit</TEXT>
</LOCKBIT0>
<LOCKBIT1>
<NAME>LB2</NAME>
<TEXT>Lockbit</TEXT>
</LOCKBIT1>
</LOCKBIT>
<IO_MODULE><MODULE_LIST>[ANALOG_COMPARATOR:AD_CONVERTER:UART:SPI:CPU:EXTERNAL_INTERRUPT:EEPROM:PORTB:PORTC:PORTD:TIMER_COUNTER_0:TIMER_COUNTER_1:WATCHDOG]</MODULE_LIST><ANALOG_COMPARATOR>
<LIST>[ACSR]</LIST>
<LINK/>
<ICON>io_analo.bmp</ICON>
<ID>AlgComp_01</ID>
<TEXT/>
<ACSR>
<NAME>ACSR</NAME>
<DESCRIPTION>Analog Comparator Control And Status Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$08</IO_ADDR>
<MEM_ADDR>$28</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>ACD</NAME>
<DESCRIPTION>Analog Comparator Disable</DESCRIPTION>
<TEXT>When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>AINBG</NAME>
<DESCRIPTION>Analog Comparator Bandgap Select</DESCRIPTION>
<TEXT>When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference” on page 42.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ACO</NAME>
<DESCRIPTION>Analog Compare Output</DESCRIPTION>
<TEXT>The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>NA</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ACI</NAME>
<DESCRIPTION>Analog Comparator Interrupt Flag</DESCRIPTION>
<TEXT>This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ACIE</NAME>
<DESCRIPTION>Analog Comparator Interrupt Enable</DESCRIPTION>
<TEXT>When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ACIC</NAME>
<DESCRIPTION>Analog Comparator Input Capture Enable</DESCRIPTION>
<TEXT>When written logic one, this bit enables the Input Capture function in Timer/Counter1 to be triggered by the analog comparator. The comparator output is in this case directly connected to the Input Capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection between the analog comparator and the Input Capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ACIS1</NAME>
<DESCRIPTION>Analog Comparator Interrupt Mode Select bit 1</DESCRIPTION>
<TEXT>These bits determine which comparator events that trigger the Analog Comparator interrupt.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ACIS0</NAME>
<DESCRIPTION>Analog Comparator Interrupt Mode Select bit 0</DESCRIPTION>
<TEXT>These bits determine which comparator events that trigger the Analog Comparator interrupt.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ACSR>
</ANALOG_COMPARATOR>
<AD_CONVERTER>
<LIST>[ADMUX:ADCSR:ADCH:ADCL]</LIST>
<LINK/>
<RULES>((IF ADMUX.ADLAR = 1) LINK [ADCH(1:0):ADCL(7:0)]); (IF ADMUX.ADLAR = 0) LINK [ADCH(7:0):ADCL(7:6)]);</RULES>
<ICON>io_analo.bmp</ICON>
<ID>ADConv_01</ID>
<TEXT>AD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 µs Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode Noise </TEXT>
<ADMUX>
<NAME>ADMUX</NAME>
<DESCRIPTION>The ADC multiplexer Selection Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$07</IO_ADDR>
<MEM_ADDR>$27</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT6>
<NAME>ADCBG</NAME>
<DESCRIPTION>ADC Bandgap Select</DESCRIPTION>
<TEXT>When this bit is set and the BOD is enabled (BODEN fuse programmed), a fixed bandgap voltage of 1.22 +- 0.05V replaces the normal input to the ADC. When this bit is cleared, the normal input pin as selected by MUX2..MUX0 is applied to the ADC.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT2>
<NAME>MUX2</NAME>
<DESCRIPTION>Analog Channel and Gain Selection Bits</DESCRIPTION>
<TEXT>The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>MUX1</NAME>
<DESCRIPTION>Analog Channel and Gain Selection Bits</DESCRIPTION>
<TEXT>The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>MUX0</NAME>
<DESCRIPTION>Analog Channel and Gain Selection Bits</DESCRIPTION>
<TEXT>The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ADMUX>
<ADCSR>
<NAME>ADCSR</NAME>
<DESCRIPTION>The ADC Control and Status register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$06</IO_ADDR>
<MEM_ADDR>$26</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>ADEN</NAME>
<DESCRIPTION>ADC Enable</DESCRIPTION>
<TEXT>Writing a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ADSC</NAME>
<DESCRIPTION>ADC Start Conversion</DESCRIPTION>
<TEXT>In Single Conversion Mode, a logical ‘1’ must be written to this bit to start each conversion. In Free Running Mode, a logical ‘1’ must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effect</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ADFR</NAME>
<DESCRIPTION>ADC Free Running Select</DESCRIPTION>
<TEXT>When this bit is set (one) the ADC operates in Free Running Mode. In this mode, the ADC samples and updates the data registers continuously. Clearing this bit (zero) will terminate Free Running Mode.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ADIF</NAME>
<DESCRIPTION>ADC Interrupt Flag</DESCRIPTION>
<TEXT>This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ADIE</NAME>
<DESCRIPTION>ADC Interrupt Enable</DESCRIPTION>
<TEXT>When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ADPS2</NAME>
<DESCRIPTION>ADC Prescaler Select Bits</DESCRIPTION>
<TEXT>These bits determine the division factor between the XTAL frequency and the input clock to the ADC.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ADPS1</NAME>
<DESCRIPTION>ADC Prescaler Select Bits</DESCRIPTION>
<TEXT>These bits determine the division factor between the XTAL frequency and the input clock to the ADC.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ADPS0</NAME>
<DESCRIPTION>ADC Prescaler Select Bits</DESCRIPTION>
<TEXT>These bits determine the division factor between the XTAL frequency and the input clock to the ADC.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ADCSR>
<ADCH>
<NAME>ADCH</NAME>
<DESCRIPTION>ADC Data Register High Byte</DESCRIPTION>
<TEXT>When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjus</TEXT>
<IO_ADDR>$05</IO_ADDR>
<MEM_ADDR>$25</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT1>
<NAME>ADC9</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ADC8</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ADCH>
<ADCL>
<NAME>ADCL</NAME>
<DESCRIPTION>ADC Data Register Low Byte</DESCRIPTION>
<TEXT>When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adj</TEXT>
<IO_ADDR>$04</IO_ADDR>
<MEM_ADDR>$24</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>ADC7</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ADC6</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ADC5</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ADC4</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ADC3</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ADC2</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ADC1</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ADC0</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ADCL>
</AD_CONVERTER>
<UART>
<LIST>[UDR:UCSRA:UCSRB:UBRRHI:UBRR]</LIST>
<LINK/>
<ICON>io_com.bmp</ICON>
<ID>Uart_01</ID>
<TEXT>The device features a full duplex (separate receive and transmit registers) Universal Asynchronous Receiver and Transmitter (UART). The main features are: • Baud Rate Generator Generates any Baud Rate • High Baud Rates at Low XTAL Frequencies • 8 or 9 Bits Data • Noise Filtering • Overrun Detection • Framing Error Detection • False Start Bit Detection • Three Separate Interrupts on TX Complete, TX Data Register Empty, and RX Complete • Multi-processor Communication Mode • Double Speed UART Mode</TEXT>
<UDR>
<NAME>UDR</NAME>
<DESCRIPTION>UART I/O Data Register</DESCRIPTION>
<TEXT>The UDR register is actually two physically separate registers sharing the same I/O address. When writing to the register, the UART Transmit Data register is written. When reading from UDR, the UART Receive Data register is read.</TEXT>
<IO_ADDR>$0C</IO_ADDR>
<MEM_ADDR>$2C</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>UDR7</NAME>
<DESCRIPTION>UART I/O Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>UDR6</NAME>
<DESCRIPTION>UART I/O Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UDR5</NAME>
<DESCRIPTION>UART I/O Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>UDR4</NAME>
<DESCRIPTION>UART I/O Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>UDR3</NAME>
<DESCRIPTION>UART I/O Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UDR2</NAME>
<DESCRIPTION>UART I/O Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UDR1</NAME>
<DESCRIPTION>UART I/O Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UDR0</NAME>
<DESCRIPTION>UART I/O Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UDR>
<UCSRA>
<NAME>UCSRA</NAME>
<DESCRIPTION>UART Control and Status register A</DESCRIPTION>
<TEXT/>
<IO_ADDR>$0B</IO_ADDR>
<MEM_ADDR>$2B</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>RXC</NAME>
<DESCRIPTION>UART Receive Complete</DESCRIPTION>
<TEXT>This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR. The bit is set regard-less of any detected framing errors. When the RXCIE bit in UCR is set, the UART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR. When interrupt-driven data reception is used, the UART Receive Complete Interrupt routine must read UDR in order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TXC</NAME>
<DESCRIPTION>UART Transmitt Complete</DESCRIPTION>
<TEXT>This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the UART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the bit</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UDRE</NAME>
<DESCRIPTION>UART Data Register Empty</DESCRIPTION>
<TEXT>This bit is set (one) when a character written to UDR is transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDRIE bit in UCR is set, the UART Transmit Complete interrupt to be executed as long as UDRE is set. UDRE is cleared by writing UDR. When interrupt-driven data transmittal is used, the UART Data Register Empty Interrupt routine must write UDR in order to clear UDRE, otherwise a new interrupt will occur once the interrupt routine terminates. UDRE is set (one) during reset to indicate that the transmitter is ready</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT5>
<BIT4>
<NAME>FE</NAME>
<DESCRIPTION>Framing Error</DESCRIPTION>
<TEXT>This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OR</NAME>
<DESCRIPTION>Overrun</DESCRIPTION>
<TEXT>This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDR register is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR is read.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT0>
<NAME>MPCM</NAME>
<DESCRIPTION>Mulit-processor Communication Mode</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UCSRA>
<UCSRB>
<NAME>UCSRB</NAME>
<DESCRIPTION>UART Control an Status register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>$0A</IO_ADDR>
<MEM_ADDR>$2A</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>RXCIE</NAME>
<DESCRIPTION>RX Complete Interrupt Enable</DESCRIPTION>
<TEXT>When this bit is set (one), a setting of the RXC bit in USR will cause the Receive Complete interrupt routine to be executed provided that global interrupts are enabled.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TXCIE</NAME>
<DESCRIPTION>TX Complete Interrupt Enable</DESCRIPTION>
<TEXT>When this bit is set (one), a setting of the TXC bit in USR will cause the Transmit Complete interrupt routine to be executed provided that global interrupts are enabled.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UDRIE</NAME>
<DESCRIPTION>UART Data Register Empty Interrupt Enable</DESCRIPTION>
<TEXT>When this bit is set (one), a setting of the UDRE bit in USR will cause the UART Data Register Empty interrupt routine to be executed provided that global interrupts are enabled.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>RXEN</NAME>
<DESCRIPTION>Receiver Enable</DESCRIPTION>
<TEXT>This bit enables the UART receiver when set (one). When the receiver is disabled, the TXC, OR and FE status flags cannot become set. If these flags are set, turning off RXEN does not cause them to be cleared.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TXEN</NAME>
<DESCRIPTION>Transmitter Enable</DESCRIPTION>
<TEXT>This bit enables the UART transmitter when set (one). When disabling the transmitter while transmitting a character, the transmitter is not disabled before the character in the shift register plus any following character in UDR has been completely transmitted.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CHR9</NAME>
<DESCRIPTION>9-bit Characters</DESCRIPTION>
<TEXT>When this bit is set (one) transmitted and received characters are 9 bit long plus start and stop bits. The 9th bit is read and written by using the RXB8 and TXB8 bits in UCR, respectively. The 9th data bit can be used as an extra stop bit or a parity bit.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>RXB8</NAME>
<DESCRIPTION>Receive Data Bit 8</DESCRIPTION>
<TEXT>When CHR9 is set (one), RXB8 is the 9th data bit of the received character.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TXB8</NAME>
<DESCRIPTION>Transmit Data Bit 8</DESCRIPTION>
<TEXT>When CHR9 is set (one), TXB8 is the 9th data bit in the character to be transmitted.</TEXT>
<ACCESS>W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UCSRB>
<UBRRHI>
<NAME>UBRRHI</NAME>
<DESCRIPTION>UART Baud Rate Register High Byte</DESCRIPTION>
<TEXT/>
<IO_ADDR>$03</IO_ADDR>
<MEM_ADDR>$23</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT3>
<NAME>UBRRHI3</NAME>
<DESCRIPTION>UART Baud Rate Register High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UBRRHI2</NAME>
<DESCRIPTION>UART Baud Rate Register High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UBRRHI1</NAME>
<DESCRIPTION>UART Baud Rate Register High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UBRRHI0</NAME>
<DESCRIPTION>UART Baud Rate Register High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UBRRHI>
<UBRR>
<NAME>UBRR</NAME>
<DESCRIPTION>UART Baud Rate Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$09</IO_ADDR>
<MEM_ADDR>$29</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>UBRR7</NAME>
<DESCRIPTION>UART Baud Rate Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>UBRR6</NAME>
<DESCRIPTION>UART Baud Rate Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UBRR5</NAME>
<DESCRIPTION>UART Baud Rate Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>UBRR4</NAME>
<DESCRIPTION>UART Baud Rate Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>UBRR3</NAME>
<DESCRIPTION>UART Baud Rate Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UBRR2</NAME>
<DESCRIPTION>UART Baud Rate Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UBRR1</NAME>
<DESCRIPTION>UART Baud Rate Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UBRR0</NAME>
<DESCRIPTION>UART Baud Rate Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UBRR>
</UART>
<SPI>
<LIST>[SPDR:SPSR:SPCR]</LIST>
<LINK/>
<ICON>io_com.bmp</ICON>
<ID/>
<TEXT>The Serial Peripheral Interface(SPI) allows high-speed synchronous data transfer between the AT90S4414/8515 and peripheral devices or between several AVR devices. The AT90S4414/8515 SPI features include the following: • Full-duplex, 3-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Four Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wakeup from Idle Mode (Slave Mode Only)</TEXT>
<SPCR>
<NAME>SPCR</NAME>
<DESCRIPTION>SPI Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$0D</IO_ADDR>
<MEM_ADDR>$2D</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>SPIE</NAME>
<DESCRIPTION>SPI Interrupt Enable</DESCRIPTION>
<TEXT>This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>SPE</NAME>
<DESCRIPTION>SPI Enable</DESCRIPTION>
<TEXT>When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DORD</NAME>
<DESCRIPTION>Data Order</DESCRIPTION>
<TEXT>When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>MSTR</NAME>
<DESCRIPTION>Master/Slave Select</DESCRIPTION>
<TEXT>This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>CPOL</NAME>
<DESCRIPTION>Clock polarity</DESCRIPTION>
<TEXT>When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CPHA</NAME>
<DESCRIPTION>Clock Phase</DESCRIPTION>
<TEXT>Refer to Figure 36 or Figure 37 for the functionality of this bit.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>SPR1</NAME>
<DESCRIPTION>SPI Clock Rate Select 1</DESCRIPTION>
<TEXT>These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SPR0</NAME>
<DESCRIPTION>SPI Clock Rate Select 0</DESCRIPTION>
<TEXT>These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SPCR>
<SPSR>
<NAME>SPSR</NAME>
<DESCRIPTION>SPI Status Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$0E</IO_ADDR>
<MEM_ADDR>$2E</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>SPIF</NAME>
<DESCRIPTION>SPI Interrupt Flag</DESCRIPTION>
<TEXT>When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR).</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>WCOL</NAME>
<DESCRIPTION>Write Collision Flag</DESCRIPTION>
<TEXT>The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
</SPSR>
<SPDR>
<NAME>SPDR</NAME>
<DESCRIPTION>SPI Data Register</DESCRIPTION>
<TEXT>The SPI Data Register is a read/write register used for data transfer between the register file and the SPI Shift register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.</TEXT>
<IO_ADDR>$0F</IO_ADDR>
<MEM_ADDR>$2F</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>SPDR7</NAME>
<DESCRIPTION>SPI Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT7>
<BIT6>
<NAME>SPDR6</NAME>
<DESCRIPTION>SPI Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT6>
<BIT5>
<NAME>SPDR5</NAME>
<DESCRIPTION>SPI Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT5>
<BIT4>
<NAME>SPDR4</NAME>
<DESCRIPTION>SPI Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT4>
<BIT3>
<NAME>SPDR3</NAME>
<DESCRIPTION>SPI Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT3>
<BIT2>
<NAME>SPDR2</NAME>
<DESCRIPTION>SPI Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT2>
<BIT1>
<NAME>SPDR1</NAME>
<DESCRIPTION>SPI Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SPDR0</NAME>
<DESCRIPTION>SPI Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SPDR>
</SPI>
<CPU>
<LIST>[SREG:SP:MCUCR:MCUSR]</LIST>
<LINK/>
<ICON>io_cpu.com</ICON>
<ID/>
<TEXT/>
<SREG>
<NAME>SREG</NAME>
<DESCRIPTION>Status Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$3F</IO_ADDR>
<MEM_ADDR>$5F</MEM_ADDR>
<ICON>io_sreg.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>I</NAME>
<DESCRIPTION>Global Interrupt Enable</DESCRIPTION>
<TEXT>The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>T</NAME>
<DESCRIPTION>Bit Copy Storage</DESCRIPTION>
<TEXT>The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>H</NAME>
<DESCRIPTION>Half Carry Flag</DESCRIPTION>
<TEXT>The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>S</NAME>
<DESCRIPTION>Sign Bit</DESCRIPTION>
<TEXT>The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>V</NAME>
<DESCRIPTION>Two's Complement Overflow Flag</DESCRIPTION>
<TEXT>The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>N</NAME>
<DESCRIPTION>Negative Flag</DESCRIPTION>
<TEXT>The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>Z</NAME>
<DESCRIPTION>Zero Flag</DESCRIPTION>
<TEXT>The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>C</NAME>
<DESCRIPTION>Carry Flag</DESCRIPTION>
<TEXT>The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SREG>
<SP>
<NAME>SP</NAME>
<DESCRIPTION>Stack Pointer</DESCRIPTION>
<TEXT>The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrup</TEXT>
<IO_ADDR>$3D</IO_ADDR>
<MEM_ADDR>$5D</MEM_ADDR>
<ICON/>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>SP7</NAME>
<DESCRIPTION>Stack pointer bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>SP6</NAME>
<DESCRIPTION>Stack pointer bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>SP5</NAME>
<DESCRIPTION>Stack pointer bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>SP4</NAME>
<DESCRIPTION>Stack pointer bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>SP3</NAME>
<DESCRIPTION>Stack pointer bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>SP2</NAME>
<DESCRIPTION>Stack pointer bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>SP1</NAME>
<DESCRIPTION>Stack pointer bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SP0</NAME>
<DESCRIPTION>Stack pointer bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SP>
<MCUCR>
<NAME>MCUCR</NAME>
<DESCRIPTION>MCU Control Register</DESCRIPTION>
<TEXT>The MCU Control Register contains control bits for general MCU functions.</TEXT>
<IO_ADDR>$35</IO_ADDR>
<MEM_ADDR>$55</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT5>
<NAME>SE</NAME>
<DESCRIPTION>Sleep Enable</DESCRIPTION>
<TEXT>The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>SM</NAME>
<DESCRIPTION>Sleep Mode Select</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ISC11</NAME>
<DESCRIPTION>Interrupt Sense Control 1 bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ISC10</NAME>
<DESCRIPTION>Interrupt Sense Control 1 bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ISC01</NAME>
<DESCRIPTION>Interrupt Sense Control 0 bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ISC00</NAME>
<DESCRIPTION>Interrupt Sense Control 0 bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</MCUCR>
<MCUSR>
<NAME>MCUSR</NAME>
<DESCRIPTION/>
<TEXT/>
<IO_ADDR>$34</IO_ADDR>
<MEM_ADDR>$54</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT3>
<NAME>WDRF</NAME>
<DESCRIPTION>Watchdog Reset Flag</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>BORF</NAME>
<DESCRIPTION>Brown-Out Reset Flag</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>EXTRF</NAME>
<DESCRIPTION>External Reset Flag</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORF</NAME>
<DESCRIPTION>Power-on Reset Flag</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</MCUSR>
</CPU>
<EXTERNAL_INTERRUPT>
<LIST>[GIMSK:GIFR]</LIST>
<LINK/>
<ICON>io_ext.bmp</ICON>
<ID/>
<TEXT/>
<GIMSK>
<NAME>GIMSK</NAME>
<DESCRIPTION>General Interrupt Mask Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$3B</IO_ADDR>
<MEM_ADDR>$5B</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>INT1</NAME>
<DESCRIPTION>External Interrupt Request 1 Enable</DESCRIPTION>
<TEXT>When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from program memory address $002. See also “External Interrupts”.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>INT0</NAME>
<DESCRIPTION>External Interrupt Request 0 Enable</DESCRIPTION>
<TEXT>When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also “External Interrupts.” • Bits 5..0 - Res: Reserved bits</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
</GIMSK>
<GIFR>
<NAME>GIFR</NAME>
<DESCRIPTION>General Interrupt Flag register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$3A</IO_ADDR>
<MEM_ADDR>$5A</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>INTF1</NAME>
<DESCRIPTION>External Interrupt Flag 1</DESCRIPTION>
<TEXT>When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit in SREG and the INT1 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $002. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>INTF0</NAME>
<DESCRIPTION>External Interrupt Flag 0</DESCRIPTION>
<TEXT>When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
</GIFR>
</EXTERNAL_INTERRUPT>
<EEPROM>
<LIST>[EEAR:EEDR:EECR]</LIST>
<LINK/>
<ICON>io_cpu.bmp</ICON>
<ID>EEPROM_02.xml</ID>
<TEXT/>
<EEAR>
<NAME>EEAR</NAME>
<DESCRIPTION>EEPROM Read/Write Access</DESCRIPTION>
<TEXT>The EEPROM access register is accessible in the I/O space. The write access time is in the range of 2.5 - 4ms, depending on the V CC voltages. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some pre-caution must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. CPU operation under these conditions is likely cause the program counter to perform unintentional jumps and eventually execute the EEPROM write code. To secure EEPROM integrity, the user is advised to use an external under-voltage reset circuit in this case. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction</TEXT>
<IO_ADDR>$1E</IO_ADDR>
<MEM_ADDR>$3E</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>EEAR7</NAME>
<DESCRIPTION>EEPROM Read/Write Access bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>EEAR6</NAME>
<DESCRIPTION>EEPROM Read/Write Access bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>EEAR5</NAME>
<DESCRIPTION>EEPROM Read/Write Access bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>EEAR4</NAME>
<DESCRIPTION>EEPROM Read/Write Access bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>EEAR3</NAME>
<DESCRIPTION>EEPROM Read/Write Access bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>EEAR2</NAME>
<DESCRIPTION>EEPROM Read/Write Access bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>EEAR1</NAME>
<DESCRIPTION>EEPROM Read/Write Access bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>EEAR0</NAME>
<DESCRIPTION>EEPROM Read/Write Access bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EEAR>
<EEDR>
<NAME>EEDR</NAME>
<DESCRIPTION>EEPROM Data Register</DESCRIPTION>
<TEXT>For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.</TEXT>
<IO_ADDR>$1D</IO_ADDR>
<MEM_ADDR>$3D</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>EEDR7</NAME>
<DESCRIPTION>EEPROM Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>EEDR6</NAME>
<DESCRIPTION>EEPROM Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>EEDR5</NAME>
<DESCRIPTION>EEPROM Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>EEDR4</NAME>
<DESCRIPTION>EEPROM Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>EEDR3</NAME>
<DESCRIPTION>EEPROM Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>EEDR2</NAME>
<DESCRIPTION>EEPROM Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>EEDR1</NAME>
<DESCRIPTION>EEPROM Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>EEDR0</NAME>
<DESCRIPTION>EEPROM Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EEDR>
<EECR>
<NAME>EECR</NAME>
<DESCRIPTION>EEPROM Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$1C</IO_ADDR>
<MEM_ADDR>$3C</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT3>
<NAME>EERIE</NAME>
<DESCRIPTION>EEProm Ready Interrupt Enable</DESCRIPTION>
<TEXT>When the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready Interrupt generates a constant interrupt when EEWE is cleared (zero).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>EEMWE</NAME>
<DESCRIPTION>EEPROM Master Write Enable</DESCRIPTION>
<TEXT>The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set(one) setting EEWE will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for a EEPROM write procedure.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>EEWE</NAME>
<DESCRIPTION>EEPROM Write Enable</DESCRIPTION>
<TEXT>The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential): 1. Wait until EEWE becomes zero. 2. Write new EEPROM address to EEARL and EEARH (optional). 3. Write new EEPROM data to EEDR (optional). 4. Write a logical one to the EEMWE bit in EECR (to be able to write a logical one to the EEMWE bit, the EEWE bit mustbewritten to zero in thesamecycle). 5. Within four clock cycles after setting EEMWE, write a logical one to EEWE. When the write access time (typically 2.5 ms at V CC =5Vor 4msatV CC = 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted or two cycles before the next instruction is executed. Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>EERE</NAME>
<DESCRIPTION>EEPROM Read Enable</DESCRIPTION>
<TEXT>The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O registers, the write operation will be interrupted, and the result is undefined.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EECR>
</EEPROM>
<PORTB>
<LIST>[PORTB:DDRB:PINB]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTB>
<NAME>PORTB</NAME>
<DESCRIPTION>Data Register, Port B</DESCRIPTION>
<TEXT/>
<IO_ADDR>$18</IO_ADDR>
<MEM_ADDR>$38</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT5>
<NAME>PORTB5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PORTB4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PORTB3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PORTB2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PORTB1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORTB0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTB>
<DDRB>
<NAME>DDRB</NAME>
<DESCRIPTION>Data Direction Register, Port B</DESCRIPTION>
<TEXT/>
<IO_ADDR>$17</IO_ADDR>
<MEM_ADDR>$37</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT5>
<NAME>DDB5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DDB4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DDB3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DDB2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DDB1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DDB0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DDRB>
<PINB>
<NAME>PINB</NAME>
<DESCRIPTION>Input Pins, Port B</DESCRIPTION>
<TEXT/>
<IO_ADDR>$16</IO_ADDR>
<MEM_ADDR>$36</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT5>
<NAME>PINB5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PINB4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PINB3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PINB2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PINB1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PINB0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PINB>
</PORTB>
<PORTC>
<LIST>[PORTC:DDRC:PINC]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTC>
<NAME>PORTC</NAME>
<DESCRIPTION>Port C Data Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$15</IO_ADDR>
<MEM_ADDR>$35</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT5>
<NAME>PORTC5</NAME>
<DESCRIPTION>Port C Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PORTC4</NAME>
<DESCRIPTION>Port C Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PORTC3</NAME>
<DESCRIPTION>Port C Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PORTC2</NAME>
<DESCRIPTION>Port C Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PORTC1</NAME>
<DESCRIPTION>Port C Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORTC0</NAME>
<DESCRIPTION>Port C Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTC>
<DDRC>
<NAME>DDRC</NAME>
<DESCRIPTION>Port C Data Direction Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$14</IO_ADDR>
<MEM_ADDR>$34</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT5>
<NAME>DDC5</NAME>
<DESCRIPTION>Port C Data Direction Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DDC4</NAME>
<DESCRIPTION>Port C Data Direction Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DDC3</NAME>
<DESCRIPTION>Port C Data Direction Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DDC2</NAME>
<DESCRIPTION>Port C Data Direction Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DDC1</NAME>
<DESCRIPTION>Port C Data Direction Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DDC0</NAME>
<DESCRIPTION>Port C Data Direction Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DDRC>
<PINC>
<NAME>PINC</NAME>
<DESCRIPTION>Port C Input Pins</DESCRIPTION>
<TEXT>The Port C Input Pins address - PINC - is not a register, and this address enables access to the physical value on each Port C pin. When reading PORTC, the Port C Data Latch is read, and when reading PINC, the logical values present on the pins are read.</TEXT>
<IO_ADDR>$13</IO_ADDR>
<MEM_ADDR>$33</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT5>
<NAME>PINC5</NAME>
<DESCRIPTION>Port C Input Pins bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PINC4</NAME>
<DESCRIPTION>Port C Input Pins bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PINC3</NAME>
<DESCRIPTION>Port C Input Pins bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PINC2</NAME>
<DESCRIPTION>Port C Input Pins bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PINC1</NAME>
<DESCRIPTION>Port C Input Pins bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PINC0</NAME>
<DESCRIPTION>Port C Input Pins bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PINC>
</PORTC>
<PORTD>
<LIST>[PORTD:DDRD:PIND]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTD>
<NAME>PORTD</NAME>
<DESCRIPTION>Port D Data Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$12</IO_ADDR>
<MEM_ADDR>$32</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PORTD7</NAME>
<DESCRIPTION>Port D Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PORTD6</NAME>
<DESCRIPTION>Port D Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PORTD5</NAME>
<DESCRIPTION>Port D Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PORTD4</NAME>
<DESCRIPTION>Port D Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PORTD3</NAME>
<DESCRIPTION>Port D Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PORTD2</NAME>
<DESCRIPTION>Port D Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PORTD1</NAME>
<DESCRIPTION>Port D Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORTD0</NAME>
<DESCRIPTION>Port D Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTD>
<DDRD>
<NAME>DDRD</NAME>
<DESCRIPTION>Port D Data Direction Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$11</IO_ADDR>
<MEM_ADDR>$31</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>DDD7</NAME>
<DESCRIPTION>Port D Data Direction Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>DDD6</NAME>
<DESCRIPTION>Port D Data Direction Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DDD5</NAME>
<DESCRIPTION>Port D Data Direction Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DDD4</NAME>
<DESCRIPTION>Port D Data Direction Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DDD3</NAME>
<DESCRIPTION>Port D Data Direction Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DDD2</NAME>
<DESCRIPTION>Port D Data Direction Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DDD1</NAME>
<DESCRIPTION>Port D Data Direction Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DDD0</NAME>
<DESCRIPTION>Port D Data Direction Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DDRD>
<PIND>
<NAME>PIND</NAME>
<DESCRIPTION>Port D Input Pins</DESCRIPTION>
<TEXT>The Port D Input Pins address - PIND - is not a register, and this address enables access to the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is read, and when reading PIND, the logical values present on the pins are read.</TEXT>
<IO_ADDR>$10</IO_ADDR>
<MEM_ADDR>$30</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PIND7</NAME>
<DESCRIPTION>Port D Input Pins bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PIND6</NAME>
<DESCRIPTION>Port D Input Pins bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PIND5</NAME>
<DESCRIPTION>Port D Input Pins bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PIND4</NAME>
<DESCRIPTION>Port D Input Pins bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PIND3</NAME>
<DESCRIPTION>Port D Input Pins bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PIND2</NAME>
<DESCRIPTION>Port D Input Pins bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PIND1</NAME>
<DESCRIPTION>Port D Input Pins bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PIND0</NAME>
<DESCRIPTION>Port D Input Pins bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PIND>
</PORTD>
<TIMER_COUNTER_0>
<LIST>[TIMSK:TIFR:TCCR0:TCNT0]</LIST>
<LINK/>
<ICON>io_timer.bmp</ICON>
<ID>t81</ID>
<TEXT>The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in “Timer/Counter0 Control Register - TCCR0” on page 35. The overflow status flag is found in “The Timer/Counter Interrupt Flag Register - TIFR” on page 29. Control signals are found in the Timer/Counter0 Control Register - TCCR0. The interrupt enable/disable settings for Timer/Counter0 are found in “The Timer/Counter Interrupt Mask Regis-ter - TIMSK” on page 28. When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportuni-ties. Similarly, the high prescaling opportuni ties make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions</TEXT>
<TIMSK>
<NAME>TIMSK</NAME>
<DESCRIPTION>Timer/Counter Interrupt Mask Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$39</IO_ADDR>
<MEM_ADDR>$59</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT1>
<NAME>TOIE0</NAME>
<DESCRIPTION>Timer/Counter0 Overflow Interrupt Enable</DESCRIPTION>
<TEXT>When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
</TIMSK>
<TIFR>
<NAME>TIFR</NAME>
<DESCRIPTION>Timer/Counter Interrupt Flag register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$38</IO_ADDR>
<MEM_ADDR>$58</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT1>
<NAME>TOV0</NAME>
<DESCRIPTION>Timer/Counter0 Overflow Flag</DESCRIPTION>
<TEXT>The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
</TIFR>
<TCCR0>
<NAME>TCCR0</NAME>
<DESCRIPTION>Timer/Counter0 Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$33</IO_ADDR>
<MEM_ADDR>$53</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT2>
<NAME>CS02</NAME>
<DESCRIPTION>Clock Select0 bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CS01</NAME>
<DESCRIPTION>Clock Select0 bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CS00</NAME>
<DESCRIPTION>Clock Select0 bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR0>
<TCNT0>
<NAME>TCNT0</NAME>
<DESCRIPTION>Timer Counter 0</DESCRIPTION>
<TEXT>The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the clock cycle following the write operation.</TEXT>
<IO_ADDR>$32</IO_ADDR>
<MEM_ADDR>$52</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TCNT07</NAME>
<DESCRIPTION>Timer Counter 0 bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TCNT06</NAME>
<DESCRIPTION>Timer Counter 0 bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TCNT05</NAME>
<DESCRIPTION>Timer Counter 0 bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TCNT04</NAME>
<DESCRIPTION>Timer Counter 0 bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TCNT03</NAME>
<DESCRIPTION>Timer Counter 0 bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCNT02</NAME>
<DESCRIPTION>Timer Counter 0 bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TCNT01</NAME>
<DESCRIPTION>Timer Counter 0 bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCNT00</NAME>
<DESCRIPTION>Timer Counter 0 bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCNT0>
</TIMER_COUNTER_0>
<TIMER_COUNTER_1>
<LIST>[TIMSK:TIFR:TCCR1A:TCCR1B:TCNT1H:TCNT1L:OCR1H:OCR1L:ICR1H:ICR1L]</LIST>
<LINK>[TCNT1H:TCNT1L];[OCR1H:OCR1L];[ICR1H:ICR1L]</LINK>
<ICON>io_timer.bmp</ICON>
<ID>t16pwm1_2.xml</ID>
<TEXT>The 16-bit Timer/Counter1 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in the specification for the Timer/Counter1 Control Registers - TCCR1A and TCCR1B. The different status flags (overflow, compare match and capture event) are found in the Timer/Counter Interrupt Flag Register - TIFR. Control signals are found in the Timer/Counter1 Control Registers - TCCR1A and TCCR1B. The interrupt enable/disable settings for Timer/Counter1 are found in the Timer/Counter Interrupt Mask Register - TIMS</TEXT>
<TIMSK>
<NAME>TIMSK</NAME>
<DESCRIPTION>Timer/Counter Interrupt Mask Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$39</IO_ADDR>
<MEM_ADDR>$59</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>TOIE1</NAME>
<DESCRIPTION>Timer/Counter1 Overflow Interrupt Enable</DESCRIPTION>
<TEXT>When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCIE1</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Match Interrupt Enable</DESCRIPTION>
<TEXT>When the OCIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a Compare match in Timer/Counter1 occurs, i.e., when the OCF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT3>
<NAME>TICIE1</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
</TIMSK>
<TIFR>
<NAME>TIFR</NAME>
<DESCRIPTION>Timer/Counter Interrupt Flag register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$38</IO_ADDR>
<MEM_ADDR>$58</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>TOV1</NAME>
<DESCRIPTION>Timer/Counter1 Overflow Flag</DESCRIPTION>
<TEXT>The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCF1</NAME>
<DESCRIPTION>Output Compare Flag 1</DESCRIPTION>
<TEXT>The OCF1 bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1 - Output Compare Register 1. OCF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1 (Timer/Counter1 Compare match Interrupt Enable), and the OCF1 are set (one), the Timer/Counter1 Compare match Interrupt is executed. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT3>
<NAME>ICF1</NAME>
<DESCRIPTION>Input Capture Flag 1</DESCRIPTION>
<TEXT>The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
</TIFR>
<TCCR1A>
<NAME>TCCR1A</NAME>
<DESCRIPTION>Timer/Counter1 Control Register A</DESCRIPTION>
<TEXT/>
<IO_ADDR>$2F</IO_ADDR>
<MEM_ADDR>$4F</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>COM11</NAME>
<DESCRIPTION>Compare Output Mode 1, bit 1</DESCRIPTION>
<TEXT>The COM11 and COM10 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output Compare pin 1. This is an alternative function to an I/O port and the corresponding direction control bit must be set (one) to control the output pin. The control configuration is shown in Table 9. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>COM10</NAME>
<DESCRIPTION>Compare Ouput Mode 1, bit 0</DESCRIPTION>
<TEXT>The COM11 and COM10 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output Compare pin 1. This is an alternative function to an I/O port and the corresponding direction control bit must be set (one) to control the output pin. The control configuration is shown in Table 9. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT1>
<NAME>PWM11</NAME>
<DESCRIPTION>Pulse Width Modulator Select Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PWM10</NAME>
<DESCRIPTION>Pulse Width Modulator Select Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR1A>
<TCCR1B>
<NAME>TCCR1B</NAME>
<DESCRIPTION>Timer/Counter1 Control Register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>$2E</IO_ADDR>
<MEM_ADDR>$4E</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>ICNC1</NAME>
<DESCRIPTION>Input Capture 1 Noise Canceler</DESCRIPTION>
<TEXT>When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ICES1</NAME>
<DESCRIPTION>Input Capture 1 Edge Select</DESCRIPTION>
<TEXT>While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT3>
<NAME>CTC1</NAME>
<DESCRIPTION>Clear Timer/Counter1 on Compare Match</DESCRIPTION>
<TEXT>When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock cycle after a compareA match. If the CTC1 control bit is cleared, Timer/Counter1 continues counting and is unaffected by a compare match. Since the compare match is detected in the CPU clock cycle following the match, this function will behave differently when a prescal-ing higher than 1 is used for the timer. When a prescaling of 1 is used, and the compareA register is set to C, the timer will count as follows if CTC1 is set: ...|C-2 |C-1 |C |0|1 |... When the prescaler is set to divide by 8, the timer will count like this: ... | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, 0, 0, 0, 0, 0, 0, 0 | ... In PWM mode, this bit has no effect</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CS12</NAME>
<DESCRIPTION>Clock Select1 bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CS11</NAME>
<DESCRIPTION>Clock Select1 bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CS10</NAME>
<DESCRIPTION>Clock Select1 bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR1B>
<TCNT1H>
<NAME>TCNT1H</NAME>
<DESCRIPTION>Timer/Counter1 High Byte</DESCRIPTION>
<TEXT>This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program. <Please refer to the datasheet</TEXT>
<IO_ADDR>$2D</IO_ADDR>
<MEM_ADDR>$4D</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TCNT1H7</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TCNT1H6</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TCNT1H5</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TCNT1H4</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TCNT1H3</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCNT1H2</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TCNT1H1</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCNT1H0</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCNT1H>
<TCNT1L>
<NAME>TCNT1L</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte</DESCRIPTION>
<TEXT>This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program.<Please refer to the datasheet</TEXT>
<IO_ADDR>$2C</IO_ADDR>
<MEM_ADDR>$4C</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TCNT1L7</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TCNT1L6</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TCNT1L5</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TCNT1L4</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TCNT1L3</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCNT1L2</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TCNT1L1</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCNT1L0</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCNT1L>
<OCR1H>
<NAME>OCR1AH</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program. <Please refer to the datasheet</TEXT>
<IO_ADDR>$2B</IO_ADDR>
<MEM_ADDR>$4B</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR1AH7</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR1AH6</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR1AH5</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR1AH4</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR1AH3</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR1AH2</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR1AH1</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR1AH0</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR1H>
<OCR1L>
<NAME>OCR1AL</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program .<Please refer to the datasheet</TEXT>
<IO_ADDR>$2A</IO_ADDR>
<MEM_ADDR>$4A</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR1AL7</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR1AL6</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR1AL5</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR1AL4</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR1AL3</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR1AL2</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR1AL1</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR1AL0</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR1L>
<ICR1H>
<NAME>ICR1H</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte</DESCRIPTION>
<TEXT>The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. <Please refer to the datashee</TEXT>
<IO_ADDR>$27</IO_ADDR>
<MEM_ADDR>$47</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>ICR1H7</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ICR1H6</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ICR1H5</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ICR1H4</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ICR1H3</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ICR1H2</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ICR1H1</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ICR1H0</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ICR1H>
<ICR1L>
<NAME>ICR1L</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte</DESCRIPTION>
<TEXT>The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. <Please refer to the datasheet</TEXT>
<IO_ADDR>$26</IO_ADDR>
<MEM_ADDR>$46</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>ICR1L7</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ICR1L6</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ICR1L5</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ICR1L4</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ICR1L3</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ICR1L2</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ICR1L1</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ICR1L0</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ICR1L>
</TIMER_COUNTER_1>
<WATCHDOG>
<LIST>[WDTCR]</LIST>
<LINK/>
<ICON>io_watch.bmp</ICON>
<ID/>
<TEXT/>
<WDTCR>
<NAME>WDTCR</NAME>
<DESCRIPTION>Watchdog Timer Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$21</IO_ADDR>
<MEM_ADDR>$41</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT4>
<NAME>WDTOE</NAME>
<ALIAS>WDDE</ALIAS>
<DESCRIPTION>RW</DESCRIPTION>
<TEXT>This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a watchdog disable procedure.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>WDE</NAME>
<DESCRIPTION>Watch Dog Enable</DESCRIPTION>
<TEXT>When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>WDP2</NAME>
<DESCRIPTION>Watch Dog Timer Prescaler bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>WDP1</NAME>
<DESCRIPTION>Watch Dog Timer Prescaler bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>WDP0</NAME>
<DESCRIPTION>Watch Dog Timer Prescaler bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</WDTCR>
</WATCHDOG>
</IO_MODULE><ICE_SETTINGS><MODULE_LIST>[SIMULATOR:STK500:STK500_2]</MODULE_LIST><SIMULATOR>
<CoreID>AVRSimCoreV2.SimCoreV2</CoreID>
<MemoryID>AVRSimMemory8bit.SimMemory8bit</MemoryID>
<InterruptID>AVRSimInterrupt.SimInterrupt</InterruptID>
<EEINTERRUPT>0x0c</EEINTERRUPT>
<EEAR_EXTRA_BIT>0</EEAR_EXTRA_BIT>
<NmbIOModules>10</NmbIOModules>
<PORTB>
<ID>AVRSimIOPort.SimIOPort</ID>
<MASK>0xff</MASK>
<TOGGLE_PIN>N</TOGGLE_PIN>
</PORTB>
<PORTC>
<ID>AVRSimIOPort.SimIOPort</ID>
<MASK>0xff</MASK>
<TOGGLE_PIN>N</TOGGLE_PIN>
</PORTC>
<PORTD>
<ID>AVRSimIOPort.SimIOPort</ID>
<MASK>0xff</MASK>
<TOGGLE_PIN>N</TOGGLE_PIN>
</PORTD>
<EXTINT0>
<ID>AVRSimIOExtInterrupt.SimIOExtInterrupt</ID>
<IntVector>0x01</IntVector>
<EnableIOAdr>0x3b</EnableIOAdr>
<EnableMask>0x40</EnableMask>
<FlagIOAdr>0x3a</FlagIOAdr>
<FlagMask>0x40</FlagMask>
<ExtPinIOAdr>0x10</ExtPinIOAdr>
<ExtPinMask>0x04</ExtPinMask>
<SenseIOAdr>0x35</SenseIOAdr>
<SenseMask>0x03</SenseMask>
</EXTINT0>
<EXTINT1>
<ID>AVRSimIOExtInterrupt.SimIOExtInterrupt</ID>
<IntVector>0x02</IntVector>
<EnableIOAdr>0x3b</EnableIOAdr>
<EnableMask>0x80</EnableMask>
<FlagIOAdr>0x3a</FlagIOAdr>
<FlagMask>0x80</FlagMask>
<ExtPinIOAdr>0x10</ExtPinIOAdr>
<ExtPinMask>0x08</ExtPinMask>
<SenseIOAdr>0x35</SenseIOAdr>
<SenseMask>0x0c</SenseMask>
</EXTINT1>
<TIMER0>
<ID>AVRSimIOTimert81.SimIOTimert81</ID>
<IntVector>0x06</IntVector>
<ExtPinIOAdr>0x10</ExtPinIOAdr>
<ExtPinMask>0x10</ExtPinMask>
</TIMER0>
<TIMER1>
<ID>AVRSimIOTimert16pwm1.SimIOTimert16pwm1</ID>
<IcpVector>0x03</IcpVector>
<CompAVector>0x04</CompAVector>
<OvfVector>0x05</OvfVector>
<CountPinAdr>0x10</CountPinAdr>
<CountPinMask>0x20</CountPinMask>
<IcpPinAdr>0x16</IcpPinAdr>
<IcpPinMask>0x01</IcpPinMask>
<OutputAAdr>0x16</OutputAAdr>
<OutputAMask>0x02</OutputAMask>
</TIMER1>
<SPI>
<ID>AVRSimIOSpi.SimIOSpi</ID>
<IntVector>0x07</IntVector>
<SCKAddress>0x16</SCKAddress>
<SCKMask>0x20</SCKMask>
<MISOAddress>0x16</MISOAddress>
<MISOMask>0x10</MISOMask>
<MOSIAddress>0x16</MOSIAddress>
<MOSIMask>0x08</MOSIMask>
<SSAddress>0x16</SSAddress>
<DIRAddress>0x17</DIRAddress>
<SSMask>0x04</SSMask>
</SPI>
<UART>
<ID>AVRSimIOUart.SimIOUart</ID>
<RXVector>0x08</RXVector>
<TXVector>0x0a</TXVector>
<UDREVector>0x09</UDREVector>
<TXPinAddress>0x10</TXPinAddress>
<TXPinMask>0x02</TXPinMask>
<RXPinAddress>0x10</RXPinAddress>
<RXPinMask>0x01</RXPinMask>
</UART>
<ANALOGCOMP>
<ID>AVRSimAC.SimIOAC</ID>
<IntVector>0x0D</IntVector>
</ANALOGCOMP>
<ADC>
<ID>AVRSimADC.SimADC</ID>
<IntVector>0x0B</IntVector>
</ADC>
<DEFAULT_SETTINGS>
<HighFuse>0x99</HighFuse>
<ExtendedFuse>0xff</ExtendedFuse>
<LowFuse>0xe1</LowFuse>
<Lockbit>0xff</Lockbit>
</DEFAULT_SETTINGS>
</SIMULATOR>
<STK500>
<DeviceId>0x51</DeviceId>
<SelfTimed>0</SelfTimed>
<FullParallel>1</FullParallel>
<Polled>1</Polled>
<FPoll>0xFF</FPoll>
<EPol1>0x00</EPol1>
<EPol2>0xFF</EPol2>
<ComLockFuseRead>0</ComLockFuseRead>
</STK500>
<STK500_2><IspEnterProgMode><timeout>200</timeout><stabDelay>100</stabDelay><cmdexeDelay>25</cmdexeDelay><synchLoops>32</synchLoops><byteDelay>0</byteDelay><pollIndex>3</pollIndex><pollValue>0x53</pollValue></IspEnterProgMode><IspLeaveProgMode><preDelay>1</preDelay><postDelay>1</postDelay></IspLeaveProgMode><IspChipErase><eraseDelay>100</eraseDelay><pollMethod>0</pollMethod></IspChipErase><IspProgramFlash><mode>0x04</mode><blockSize>128</blockSize><delay>12</delay><cmd1>0x40</cmd1><cmd2>0x00</cmd2><cmd3>0x20</cmd3><pollVal1>0xFF</pollVal1><pollVal2>0x00</pollVal2></IspProgramFlash><IspProgramEeprom><mode>0x04</mode><blockSize>128</blockSize><delay>12</delay><cmd1>0xC0</cmd1><cmd2>0x00</cmd2><cmd3>0xA0</cmd3><pollVal1>0x00</pollVal1><pollVal2>0xFF</pollVal2></IspProgramEeprom><IspReadFlash><blockSize>256</blockSize></IspReadFlash><IspReadEeprom><blockSize>256</blockSize></IspReadEeprom><IspReadFuse><pollIndex>4</pollIndex></IspReadFuse><IspReadLock><pollIndex>4</pollIndex></IspReadLock><IspReadSign><pollIndex>4</pollIndex></IspReadSign><IspReadOsccal><pollIndex>4</pollIndex></IspReadOsccal><PPControlStack>0x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x00</PPControlStack><PpEnterProgMode><stabDelay>100</stabDelay><progModeDelay>0</progModeDelay><latchCycles>0</latchCycles><toggleVtg>0</toggleVtg><powerOffDelay>0</powerOffDelay><resetDelayMs>0</resetDelayMs><resetDelayUs>0</resetDelayUs></PpEnterProgMode><PpLeaveProgMode><stabDelay>15</stabDelay><resetDelay>15</resetDelay></PpLeaveProgMode><PpChipErase><pulseWidth>15</pulseWidth><pollTimeout>0</pollTimeout></PpChipErase><PpProgramFlash><pollTimeout>5</pollTimeout><mode>0x00</mode><blockSize>256</blockSize></PpProgramFlash><PpReadFlash><blockSize>256</blockSize></PpReadFlash><PpProgramEeprom><pollTimeout>5</pollTimeout><mode>0x00</mode><blockSize>256</blockSize></PpProgramEeprom><PpReadEeprom><blockSize>256</blockSize></PpReadEeprom><PpProgramFuse><pulseWidth>2</pulseWidth><pollTimeout>0</pollTimeout></PpProgramFuse><PpProgramLock><pulseWidth>0</pulseWidth><pollTimeout>1</pollTimeout></PpProgramLock></STK500_2></ICE_SETTINGS></AVRPART>
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