#define CpSC		15			/* System Control */

/*
 * CpCACHERANGE opcode2 fields for MCRR instruction (armv6)
 */
#define	CpCACHERANGEinvi	5		/* invalidate instruction  */
#define	CpCACHERANGEinvd	6		/* invalidate data */
#define CpCACHERANGEdwb		12		/* writeback */
#define CpCACHERANGEdwbi	14		/* writeback+invalidate */

#define MCRR(coproc, op, rd, rn, crm) \
	WORD $(0xec400000|(rn)<<16|(rd)<<12|(coproc)<<8|(op)<<4|(crm))

TEXT cacheflush(SB),7,$0
	MOVW R0, R1
	MOVW 4(FP), R2
	MCRR(CpSC, 0, 2, 1, CpCACHERANGEdwb)
	MCRR(CpSC, 0, 2, 1, CpCACHERANGEinvi)
	RET