Plan 9 from Bell Labs’s /usr/web/sources/extra/9hist/ss/mem.h

Copyright © 2021 Plan 9 Foundation.
Distributed under the MIT License.
Download the Plan 9 distribution.


## diffname ss/mem.h 1990/1223
## diff -e /dev/null /n/bootesdump/1990/1223/sys/src/9/sparc/mem.h
0a
/*
 * Memory and machine-specific definitions.  Used in C and assembler.
 */

/*
 * Sizes
 */

#define	BI2BY		8			/* bits per byte */
#define BI2WD		32			/* bits per word */
#define	BY2WD		4			/* bytes per word */
#define	BY2PG		4096			/* bytes per page */
#define	WD2PG		(BY2PG/BY2WD)		/* words per page */
#define	PGSHIFT		12			/* log(BY2PG) */

#define	MAXMACH		1			/* max # cpus system can run */

/*
 * Time
 */
#define	HZ		(60)			/* clock frequency */
#define	MS2HZ		(1000/HZ)		/* millisec per clock tick */
#define	TK2SEC(t)	((t)/HZ)		/* ticks to seconds */
#define	TK2MS(t)	((((ulong)(t))*1000)/HZ)	/* ticks to milliseconds */
#define	MS2TK(t)	((((ulong)(t))*HZ)/1000)	/* milliseconds to ticks */

/*
 * SR bits
 */
#define SUPER		0x2000
#define SPL(n)		(n<<8)

/*
 * CACR
 */
#define	CCLEAR		0x08
#define	CENABLE		0x01

/*
 * Magic registers
 */

#define	MACH		28		/* R28 is m-> */
#define	USER		27		/* R27 is u-> */

/*
 * Fundamental addresses
 */

#define	USERADDR	0x80000000
#define	UREGADDR	(USERADDR+BY2PG-(2+4+2+(8+8+1)*BY2WD))

/*
 * Devices poked during bootstrap
 */
#define	TACADDR		0x40600000
#define	MOUSE		0x40200000

/*
 * MMU
 */

#define	VAMASK	0x1FFFFFFF

/*
 * MMU entries
 */
#define	PTEVALID	(1<<31)
#define	PTEWRITE	(1<<30)
#define	PTEKERNEL	(1<<29)
#define	PTENOCACHE	(1<<28)
#define	PTEMAINMEM	(0<<26)
#define	PTEIO		(1<<26)
#define	PTEACCESS	(1<<25)
#define	PTEMODIFY	(1<<24)

#define	PTERONLY	0		/* BUG */
#define	INVALIDPTE	0
#define	PPN(pa)		((pa>>12)&0xFFFF)

#define	KMAP	((unsigned long *)0xD0000000)
#define	UMAP	((unsigned long *)0x50000000)

/*
 * Virtual addresses
 */
#define	VTAG(va)	((va>>22)&0x03F)
#define	VPN(va)		((va>>13)&0x1FF)

#define	PARAM		((char*)0x40500000)
#define	TLBFLUSH_	0x01

/*
 * Address spaces
 */

#define	UZERO	0x00000000			/* base of user address space */
#define	UTZERO	(UZERO+BY2PG)		/* first address in user text */
#define	TSTKTOP	0x10000000		/* end of new stack in sysexec */
#define	USTKTOP	(TSTKTOP-100*BY2PG)	/* byte just beyond user stack */
#define	KZERO	0x10000000		/* base of kernel address space */
#define	KTZERO	(KZERO+4*BY2PG)		/* first address in kernel text */
#define	USTACKSIZE	(4*1024*1024)	/* size of user stack */

#define	NSEG		5
#define	MACHSIZE	4096
.
## diffname ss/mem.h 1990/1226
## diff -e /n/bootesdump/1990/1223/sys/src/9/sparc/mem.h /n/bootesdump/1990/1226/sys/src/9/sparc/mem.h
100,101c
#define	USTKTOP	(TSTKTOP-32*BY2PG)	/* byte just beyond user stack */
#define	KZERO	0xE0000000		/* base of kernel address space */
.
97c
#define	UZERO	0x00000000		/* base of user address space */
.
84a
 * Weird addresses in various ASI's
 */
#define	CACHETAGS	0x80000000		/* ASI 2 */
#define	SER		0x60000000		/* ASI 2 */
#define	SEVAR		0x60000004		/* ASI 2 */

/*
.
77d
68a
#define	PTERONLY	(0<<30)
.
63,64d
61a
#define	INVALIDSEGM	0xFFFC0000	/* highest seg of VA reserved as invalid */
#define	INVALIDPMEG	0x7F
#define	SCREENSEGM	0xFFF80000
#define	SCREENPMEG	0x7E
#define	ROMSEGM		0xFFE80000
#define	ROMEND		0xFFEA0000
#define	PG2ROM		((ROMEND-ROMSEGM)/BY2PG)
#define	IOSEGM0		ROMSEGM		/* see mmuinit() */
#define	NIOSEGM		((SCREENSEGM-ROMSEGM)/BY2SEGM)
#define	IOPMEG0		(SCREENPMEG-NIOSEGM)
#define	IOSEGM		ROMEND
#define	IOEND		SCREENSEGM
.
60c
 * MMU regions
.
58a
#define	VAMASK		0x1FFFFFFF
#define	NPMEG		(1<<12)
#define	BY2SEGM		(1<<18)
#define	PG2SEGM		(1<<6)
#define	NTLBPID		(NCONTEXT+1)
#define	NCONTEXT	8
#define	CONTEXT		0x30000000	/* in ASI 2 */

.
56,57d
54c
 * MMU
.
50,51c
#define	USERADDR	0xE0000000
#define	UREGADDR	(USERADDR+BY2PG-((32+5)*BY2WD))
#define	BOOTSTACK	(KTZERO-0*BY2PG)
#define	TRAPS		(KTZERO-2*BY2PG)
.
43,44c
#define	MACH		6		/* R6 is m-> */
#define	USER		5		/* R5 is u-> */
.
34,39d
30c
#define	PSREC		0x00002000
#define	PSREF		0x00001000
#define PSRSUPER	0x00000080
#define PSRPSUPER	0x00000040
#define	PSRET		0x00000020
.
28c
 * PSR bits
.
## diffname ss/mem.h 1990/1227
## diff -e /n/bootesdump/1990/1226/sys/src/9/sparc/mem.h /n/bootesdump/1990/1227/sys/src/9/sparc/mem.h
57c
#define	VAMASK		0x3FFFFFFF
.
21c
#define	HZ		20			/* clock frequency */
.
## diffname ss/mem.h 1991/0108
## diff -e /n/bootesdump/1990/1227/sys/src/9/sparc/mem.h /n/bootesdump/1991/0108/sys/src/9/sparc/mem.h
79a
#define	LANCESEGM	(16*1024*1024-BY2SEGM)
#define	LANCEPMEG	(IOSEGM0-1)
#define	TOPPMEG		LANCEPMEG
.
## diffname ss/mem.h 1991/0110
## diff -e /n/bootesdump/1991/0108/sys/src/9/sparc/mem.h /n/bootesdump/1991/0110/sys/src/9/sparc/mem.h
108a
#define	ASER		0x60000008		/* ASI 2 */
#define	ASEVAR		0x6000000C		/* ASI 2 */
.
100,102d
80,82c
#define	TOPPMEG		IOPMEG0
.
61c
#define	NTLBPID		(1+NCONTEXT)	/* TLBPID 0 is unallocated */
.
## diffname ss/mem.h 1991/0111
## diff -e /n/bootesdump/1991/0110/sys/src/9/sparc/mem.h /n/bootesdump/1991/0111/sys/src/9/sparc/mem.h
105a
#define	ENAB		0x40000000		/* ASI 2 */
#define	ENABCACHE	0x10
#define	ENABRESET	0x04
.
101a
#define	CACHEDATA	0x90000000		/* ASI 2 */
.
## diffname ss/mem.h 1991/0112
## diff -e /n/bootesdump/1991/0111/sys/src/9/sparc/mem.h /n/bootesdump/1991/0112/sys/src/9/sparc/mem.h
49c
#define	UREGADDR	(USERADDR+BY2PG-((32+6)*BY2WD))
.
## diffname ss/mem.h 1991/0404
## diff -e /n/bootesdump/1991/0201/sys/src/9/sparc/mem.h /n/bootesdump/1991/0404/sys/src/9/slc/mem.h
133a

#define isphys(x) ((((ulong)(x)&0xF0000000) == KZERO)
.
## diffname ss/mem.h 1991/0411
## diff -e /n/bootesdump/1991/0404/sys/src/9/slc/mem.h /n/bootesdump/1991/0411/sys/src/9/slc/mem.h
135c
#define isphys(x) (((ulong)(x)&0xF0000000) == KZERO)
.
## diffname ss/mem.h 1991/0523
## diff -e /n/bootesdump/1991/0411/sys/src/9/slc/mem.h /n/bootesdump/1991/0523/sys/src/9/slc/mem.h
127c
#define TSTKSIZ 32
#define	USTKTOP	(TSTKTOP-TSTKSIZ*BY2PG)	/* byte just beyond user stack */
.
## diffname ss/mem.h 1991/0605
## diff -e /n/bootesdump/1991/0523/sys/src/9/slc/mem.h /n/bootesdump/1991/0605/sys/src/9/slc/mem.h
133d
131c
#define	USTKSIZE	(4*1024*1024)	/* size of user stack */
.
## diffname ss/mem.h 1991/0606
## diff -e /n/bootesdump/1991/0605/sys/src/9/slc/mem.h /n/bootesdump/1991/0606/sys/src/9/slc/mem.h
14a
#define PGROUND(s)	(((s)+(BY2PG-1))&~(BY2PG-1))
.
## diffname ss/mem.h 1991/0607
## diff -e /n/bootesdump/1991/0606/sys/src/9/slc/mem.h /n/bootesdump/1991/0607/sys/src/9/slc/mem.h
94a
#define PTEUNCACHED	0
.
## diffname ss/mem.h 1991/0706
## diff -e /n/bootesdump/1991/0607/sys/src/9/slc/mem.h /n/bootesdump/1991/0706/sys/src/9/slc/mem.h
95a
#define PTEMAPMEM	(1024*1024)	
#define	PTEPERTAB	(PTEMAPMEM/BY2PG)
#define SEGMAPSIZE	16
.
## diffname ss/mem.h 1992/0722
## diff -e /n/bootesdump/1991/0706/sys/src/9/slc/mem.h /n/bootesdump/1992/0722/sys/src/9/slc/mem.h
122,123c
/*
 * Rom addresses
 */
#define	PUTCXSEGM	0xFFE80118
.
114a
#define	VACLINESZ	16			/* cache line size */
#define	VACSIZE		(1<<16)			/* total cache size */
.
74c
#define	ROMEND		0xFFEC0000
.
## diffname ss/mem.h 1992/0807
## diff -e /n/bootesdump/1992/0807/sys/src/9/slc/mem.h /n/bootesdump/1992/0807/sys/src/9/ss/mem.h
143,144d
132d
125,129d
115,116c
#define	ENABCACHE	0x10
#define ENABDMA		0x20
.
113d
72c
#define	SCREENPMEG	(conf.npmeg-2)
.
70c
#define	INVALIDPMEG	(conf.npmeg-1)
.
62,63c
#define	NTLBPID		(1+MAXCONTEXT)	/* TLBPID 0 is unallocated */
#define	MAXCONTEXT	16
.
59d
## diffname ss/mem.h 1992/0809
## diff -e /n/bootesdump/1992/0807/sys/src/9/ss/mem.h /n/bootesdump/1992/0809/sys/src/9/ss/mem.h
94a

.
93a
#define PTEPROBEMEM	(PTEVALID|PTEKERNEL|PTENOCACHE|PTEWRITE|PTEMAINMEM)
.
## diffname ss/mem.h 1992/0812
## diff -e /n/bootesdump/1992/0809/sys/src/9/ss/mem.h /n/bootesdump/1992/0812/sys/src/9/ss/mem.h
107,113c
#define	CACHETAGS	0x80000000
#define	CACHEDATA	0x90000000
#define	SER		0x60000000
#define	SEVAR		0x60000004
#define	ASER		0x60000008
#define	ASEVAR		0x6000000C
#define	ENAB		0x40000000
.
105c
 * Weird addresses etc. in System ASI (2)
.
94a
#define PTEPROBEIO	(PTEVALID|PTEKERNEL|PTENOCACHE|PTEWRITE|PTEIO)
.
75,79c
#define	NIOSEGM		((MB/BY2SEGM) + 4)	/* 1M for screen + overhead */
#define	IOSEGM0		(ROMSEGM-NIOSEGM*BY2SEGM)
#define	IOPMEG0		(ROMPMEG-NIOSEGM)
#define	IOEND		ROMSEGM
.
70,71c
#define	ROMPMEG		(conf.npmeg-2)
.
## diffname ss/mem.h 1992/0829
## diff -e /n/bootesdump/1992/0812/sys/src/9/ss/mem.h /n/bootesdump/1992/0829/sys/src/9/ss/mem.h
74c
#define	NIOSEGM		((MB/BY2SEGM) + 8)	/* 1M for screen + overhead */
.
## diffname ss/mem.h 1992/0911
## diff -e /n/bootesdump/1992/0829/sys/src/9/ss/mem.h /n/bootesdump/1992/0911/sys/src/9/ss/mem.h
70,78c
#define IOSEGSIZE	(MB + 2*MB)	/* 1 meg for screen plus overhead */	
#define IOSEGM		(INVALIDSEGM - IOSEGSIZE)
.
61,62d
## diffname ss/mem.h 1992/0912
## diff -e /n/bootesdump/1992/0911/sys/src/9/ss/mem.h /n/bootesdump/1992/0912/sys/src/9/ss/mem.h
92c
#define	PPN(pa)		(((pa)>>12)&0xFFFF)
.
89c
#define SEGMAPSIZE	128
.
22c
#define	HZ		50			/* clock frequency */
.
## diffname ss/mem.h 1993/0501 # deleted
## diff -e /n/bootesdump/1992/0912/sys/src/9/ss/mem.h /n/fornaxdump/1993/0501/sys/src/brazil/ss/mem.h
1,126d

Bell Labs OSI certified Powered by Plan 9

(Return to Plan 9 Home Page)

Copyright © 2021 Plan 9 Foundation. All Rights Reserved.
Comments to webmaster@9p.io.