enum {
Mhz = 1000*1000,
};
/*
* duarts, frequency and registers
*/
#define DUARTFREQ 3672000
/*
* interrupt levels on CPU boards.
*/
enum
{
ILmin = 2,
ILpci = 2,
ILehci = 3,
ILenet1 = 4, /* arge1 @ 0x19:: w switch */
ILenet0 = 5, /* arge0 @ 0x1a:: */
ILduart0 = 6, /* actually APB, uart is subintr 3 */
ILclock = 7,
ILmax = 7,
ILshift = 8,
};
#define Rstblockbase (ulong *)KSEG1ADDR(0x18060000)
#define Rstwdogctl (ulong *)KSEG1ADDR(0x18060008)
#define Wdoglast (1 << 31)
#define Wdogmask 3
#define Wdognoaction 0
#define Wdoggpintr 1
#define Wdognmi 2
#define Wdogreset 3
#define Rstwdogtimer (ulong *)KSEG1ADDR(0x1806000c)
/*
* APB interrupt status and mask register and interrupt bits
*/
#define Apbintrsts (ulong *)KSEG1ADDR(0x18060010)
#define Apbintrmask (ulong *)KSEG1ADDR(0x18060014)
#define Apbintrtimer 0
#define Apbintrerror 1
#define Apbintrgpio 2
#define Apbintruart 3
#define Apbintrwatchdog 4
#define Apbintrperf 5
#define Apbintrohci 6
#define Apbintrdma 7
#define Pciintrsts (ulong *)KSEG1ADDR(0x18060018)
#define Pciintrmask (ulong *)KSEG1ADDR(0x1806001C)
#define PCI_INTR_CORE (1 << 4)
#define Reset (ulong *)KSEG1ADDR(0x18060024)
#define Rstfullchip (1 << 24) /* same as pulling the reset pin */
#define Rstcpucold (1 << 20) /* cold reset */
#define Rstge1mac (1 << 13)
#define Rstge1phy (1 << 12)
#define Rstge0mac (1 << 9)
#define Rstge0phy (1 << 8)
#define Rstusbohcidll (1 << 6)
#define Rstusbhost (1 << 5)
#define Rstusbphy (1 << 4)
#define Rstpcibus (1 << 1)
#define Rstpcicore (1 << 0)
/*
* mostly PCI from here on
*/
typedef struct Pcisiz Pcisiz;
typedef struct Pcidev Pcidev;
typedef struct Vctl Vctl;
struct Vctl {
Vctl* next; /* handlers on this vector */
char name[KNAMELEN]; /* of driver */
int isintr; /* interrupt or fault/trap */
int irq;
int tbdf;
int (*isr)(int); /* get isr bit for this irq */
int (*eoi)(int); /* eoi */
void (*f)(Ureg*, void*); /* handler to call */
void* a; /* argument to call it with */
};
enum {
BusCBUS = 0, /* Corollary CBUS */
BusCBUSII, /* Corollary CBUS II */
BusEISA, /* Extended ISA */
BusFUTURE, /* IEEE Futurebus */
BusINTERN, /* Internal bus */
BusISA, /* Industry Standard Architecture */
BusMBI, /* Multibus I */
BusMBII, /* Multibus II */
BusMCA, /* Micro Channel Architecture */
BusMPI, /* MPI */
BusMPSA, /* MPSA */
BusNUBUS, /* Apple Macintosh NuBus */
BusPCI, /* Peripheral Component Interconnect */
BusPCMCIA, /* PC Memory Card International Association */
BusTC, /* DEC TurboChannel */
BusVL, /* VESA Local bus */
BusVME, /* VMEbus */
BusXPRESS, /* Express System Bus */
};
#define MKBUS(t,b,d,f) (((t)<<24)|(((b)&0xFF)<<16)|(((d)&0x1F)<<11)|(((f)&0x07)<<8))
#define BUSFNO(tbdf) (((tbdf)>>8)&0x07)
#define BUSDNO(tbdf) (((tbdf)>>11)&0x1F)
#define BUSBNO(tbdf) (((tbdf)>>16)&0xFF)
#define BUSTYPE(tbdf) ((tbdf)>>24)
#define BUSBDF(tbdf) ((tbdf)&0x00FFFF00)
#define BUSUNKNOWN (-1)
enum {
MaxEISA = 16,
CfgEISA = 0xC80,
};
/*
* PCI support code.
*/
enum { /* type 0 & type 1 pre-defined header */
PciVID = 0x00, /* vendor ID */
PciDID = 0x02, /* device ID */
PciPCR = 0x04, /* command */
PciPSR = 0x06, /* status */
PciRID = 0x08, /* revision ID */
PciCCRp = 0x09, /* programming interface class code */
PciCCRu = 0x0A, /* sub-class code */
PciCCRb = 0x0B, /* base class code */
PciCLS = 0x0C, /* cache line size */
PciLTR = 0x0D, /* latency timer */
PciHDT = 0x0E, /* header type */
PciBST = 0x0F, /* BIST */
PciBAR0 = 0x10, /* base address */
PciBAR1 = 0x14,
PciINTL = 0x3C, /* interrupt line */
PciINTP = 0x3D, /* interrupt pin */
};
/* ccrb (base class code) values; controller types */
enum {
Pcibcpci1 = 0, /* pci 1.0; no class codes defined */
Pcibcstore = 1, /* mass storage */
Pcibcnet = 2, /* network */
Pcibcdisp = 3, /* display */
Pcibcmmedia = 4, /* multimedia */
Pcibcmem = 5, /* memory */
Pcibcbridge = 6, /* bridge */
Pcibccomm = 7, /* simple comms (e.g., serial) */
Pcibcbasesys = 8, /* base system */
Pcibcinput = 9, /* input */
Pcibcdock = 0xa, /* docking stations */
Pcibcproc = 0xb, /* processors */
Pcibcserial = 0xc, /* serial bus (e.g., USB) */
Pcibcwireless = 0xd, /* wireless */
Pcibcintell = 0xe, /* intelligent i/o */
Pcibcsatcom = 0xf, /* satellite comms */
Pcibccrypto = 0x10, /* encryption/decryption */
Pcibcdacq = 0x11, /* data acquisition & signal proc. */
};
/* ccru (sub-class code) values; common cases only */
enum {
/* mass storage */
Pciscscsi = 0, /* SCSI */
Pciscide = 1, /* IDE (ATA) */
Pciscsata = 6, /* SATA */
/* network */
Pciscether = 0, /* Ethernet */
/* display */
Pciscvga = 0, /* VGA */
Pciscxga = 1, /* XGA */
Pcisc3d = 2, /* 3D */
/* bridges */
Pcischostpci = 0, /* host/pci */
Pciscpcicpci = 1, /* pci/pci */
/* simple comms */
Pciscserial = 0, /* 16450, etc. */
Pciscmultiser = 1, /* multiport serial */
/* serial bus */
Pciscusb = 3, /* USB */
};
enum { /* type 0 pre-defined header */
PciCIS = 0x28, /* cardbus CIS pointer */
PciSVID = 0x2C, /* subsystem vendor ID */
PciSID = 0x2E, /* cardbus CIS pointer */
PciEBAR0 = 0x30, /* expansion ROM base address */
PciMGNT = 0x3E, /* burst period length */
PciMLT = 0x3F, /* maximum latency between bursts */
};
enum { /* type 1 pre-defined header */
PciPBN = 0x18, /* primary bus number */
PciSBN = 0x19, /* secondary bus number */
PciUBN = 0x1A, /* subordinate bus number */
PciSLTR = 0x1B, /* secondary latency timer */
PciIBR = 0x1C, /* I/O base */
PciILR = 0x1D, /* I/O limit */
PciSPSR = 0x1E, /* secondary status */
PciMBR = 0x20, /* memory base */
PciMLR = 0x22, /* memory limit */
PciPMBR = 0x24, /* prefetchable memory base */
PciPMLR = 0x26, /* prefetchable memory limit */
PciPUBR = 0x28, /* prefetchable base upper 32 bits */
PciPULR = 0x2C, /* prefetchable limit upper 32 bits */
PciIUBR = 0x30, /* I/O base upper 16 bits */
PciIULR = 0x32, /* I/O limit upper 16 bits */
PciEBAR1 = 0x28, /* expansion ROM base address */
PciBCR = 0x3E, /* bridge control register */
};
enum { /* type 2 pre-defined header */
PciCBExCA = 0x10,
PciCBSPSR = 0x16,
PciCBPBN = 0x18, /* primary bus number */
PciCBSBN = 0x19, /* secondary bus number */
PciCBUBN = 0x1A, /* subordinate bus number */
PciCBSLTR = 0x1B, /* secondary latency timer */
PciCBMBR0 = 0x1C,
PciCBMLR0 = 0x20,
PciCBMBR1 = 0x24,
PciCBMLR1 = 0x28,
PciCBIBR0 = 0x2C, /* I/O base */
PciCBILR0 = 0x30, /* I/O limit */
PciCBIBR1 = 0x34, /* I/O base */
PciCBILR1 = 0x38, /* I/O limit */
PciCBSVID = 0x40, /* subsystem vendor ID */
PciCBSID = 0x42, /* subsystem ID */
PciCBLMBAR = 0x44, /* legacy mode base address */
};
struct Pcisiz
{
Pcidev* dev;
int siz;
int bar;
};
struct Pcidev
{
int tbdf; /* type+bus+device+function */
ushort vid; /* vendor ID */
ushort did; /* device ID */
ushort pcr;
uchar rid;
uchar ccrp;
uchar ccru;
uchar ccrb;
uchar cls;
uchar ltr;
struct {
ulong bar; /* base address */
int size;
} mem[6];
struct {
ulong bar;
int size;
} rom;
uchar intl; /* interrupt line */
Pcidev* list;
Pcidev* link; /* next device on this bno */
Pcidev* bridge; /* down a bus */
struct {
ulong bar;
int size;
} ioa, mema;
int pmrb; /* power management register block */
};
enum {
/* vendor ids */
Vatiamd = 0x1002,
Vintel = 0x8086,
Vjmicron= 0x197b,
Vmarvell= 0x1b4b,
Vmyricom= 0x14c1,
};
#define PCIWINDOW 0
#define PCIWADDR(va) (PADDR(va)+PCIWINDOW)
#define ISAWINDOW 0
#define ISAWADDR(va) (PADDR(va)+ISAWINDOW)
/* SMBus transactions */
enum
{
SMBquick, /* sends address only */
/* write */
SMBsend, /* sends address and cmd */
SMBbytewrite, /* sends address and cmd and 1 byte */
SMBwordwrite, /* sends address and cmd and 2 bytes */
/* read */
SMBrecv, /* sends address, recvs 1 byte */
SMBbyteread, /* sends address and cmd, recv's byte */
SMBwordread, /* sends address and cmd, recv's 2 bytes */
};
typedef struct SMBus SMBus;
struct SMBus {
QLock; /* mutex */
Rendez r; /* rendezvous point for completion interrupts */
void *arg; /* implementation dependent */
ulong base; /* port or memory base of smbus */
int busy;
void (*transact)(SMBus*, int, int, int, uchar*);
};
#pragma varargck type "T" int
#pragma varargck type "T" uint
|
